Search Results for ultra-high resolution

This article provides an overview of how to use the scanning electron microscope (SEM) for imaging integrated circuits. The discussion covers the principles of operation and practical techniques of the SEM. The techniques include sample mounting, sample preparation, sputter coating, sample tilt and image composition, focus and astigmatism correction, dynamic focus and image correction, raster alignment, and adjusting brightness and contrast. The article also provides information on achieving ultra-high resolution in the SEM. It concludes with information on the general characteristics and applications of environmental SEM.

This chapter summarizes critical gaps and long-term needs in failure analysis technology as it relates to logic and memory devices and IC packages. It assesses the impact of vertical integration, new materials, and expansion in the third dimension on volume analysis, sample preparation and measurement methods, and cross-sectioning and imaging.

This chapter assesses the capabilities and limitations of electric fault isolation (EFI) technology, the measurement challenges associated with new device architectures, and the pathways for improvement in emission microscopy, laser stimulation, and optical probing. It also assesses the factors that influence signal strength, spatial and timing resolution, and alignment accuracy between signal response images and the physical layout of the IC.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.

This article reviews the basic physics behind active photon injection for local photocurrent generation in silicon and thermal laser stimulation along with standard scanning optical microscopy failure analysis tools. The discussion includes several models for understanding the local thermal effects on metallic lines, junctions, and complete devices. The article also provides a description and case study examples of multiple photocurrent and thermal injection techniques. The photocurrent examples are based on Optical Beam-Induced Current and Light-Induced Voltage Alteration. The thermal stimulus examples are Optical Beam-Induced Resistance Change/Thermally-Induced Voltage Alteration and Seebeck Effect Imaging. Lastly, the article discusses the application of solid immersion lenses to improve spatial resolution.

Laser Voltage Probing (LVP) is a key enabling technology that has matured into a well-established and essential analytical optical technique that is crucial for observing and evaluating internal circuit activity. This article begins by providing an overview on LVP history and LVP theory, providing information on electro-optical effects and free-carrier effects. It then focuses on commercially available continuous wave LVP systems. Alternative optoelectronic imaging and probing technologies for fault isolation, namely frequency mapping and laser voltage tracing, are also discussed. The subsequent section provides information on the use of Visible Laser Probing. The article closes with some common LVP observations/considerations and limitations and future work concerning LVP.

The ultimate goal of the failure analysis process is to find physical evidence that can identify the root cause of the failure. Transmission electron microscopy (TEM) has emerged as a powerful tool to characterize subtle defects. This article discusses the sample preparation procedures based on focused ion beam milling used for TEM sample preparation. It describes the principles behind commonly used imaging modes in semiconductor failure analysis and how these operation modes can be utilized to selectively maximize signal from specific beam-specimen interactions to generate useful information about the defect. Various elemental analysis techniques, namely energy dispersive spectroscopy, electron energy loss spectroscopy, and energy-filtered TEM, are described using examples encountered in failure analysis. The origin of different image contrast mechanisms, their interpretation, and analytical techniques for composition analysis are discussed. The article also provides information on the use of off-axis electron holography technique in failure analysis.

Photon emission (PE) is one of the major optical techniques for contactless isolation of functional faults in integrated circuits (ICs) in full electrical operation. This article describes the fundamental mechanisms of PE in silicon based ICs. It presents the opportunities of contactless characterization for the most important electronic device, the MOS - Field Effect Transistor, the heart of ICs and their basic digital element, the CMOS inverter. The article discusses the specification and selection of detectors for proper PE applications. The main topics are image resolution, sensitivity, and spectral range of the detectors. The article also discusses the value and application of spectral information in the PE signal. It describes state of the art IC technologies. Finally, the article discusses the applications of PE in ICs and also I/O devices, integrated bipolar transistors in BiCMOS technologies, and parasitic bipolar effects like latch up.

An architectural shift to buried power rails (BPRs) with backside power delivery (BPD) is on the horizon as CMOS technology approaches the 2 nm node. The obstruction created by the presence of BPD networks obsoletes many of the electrical fault isolation (EFI) techniques that have been used for the past few decades and severely degrades the performance of others. This chapter provides an overview of EFI methods that are still applicable to ICs with BPD networks, including e-beam and atomic force probing, x-ray and magnetic field imaging, and lock-in thermography. It assesses the technical challenges of each method as well as the potential for improvement.

Scanning Probe Microscope (SPM) has an increasing important role in the development of nanoscale semiconductor technologies. This article presents a detailed discussion on various SPM techniques including Atomic Force Microscopy (AFM), Scanning Kelvin Probe Microscopy, Scanning Capacitance Microscopy, Scanning Spreading Resistance Microscopy, Conductive-AFM, Magnetic Force Microscopy, Scanning Surface Photo Voltage Microscopy, and Scanning Microwave Impedance Microscopy. An overview of each SPM technique is given along with examples of how each is used in the development of novel technologies, the monitoring of manufacturing processes, and the failure analysis of nanoscale semiconductor devices.

This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

With the commercialization of heavier and lighter ion beams, adoption of focused ion beam (FIB) use for analysis of challenging regions of interest (ROI) has grown. In this chapter, the authors focus on highlighting commercially available and complementary FIB technologies and their implementation challenges and application trends.

This chapter provides perspective on the physical dimensions associated with the microstructure of steel and the instruments that reveal grain size, morphology, phase distributions, crystal defects, and chemical composition, from which properties and behaviors derive. The chapter also reviews the definitions and classifications used to identify and differentiate commercial steels, including the AISI/SAE and UNS designation systems.

Transmitted-light methods reveal more details of the morphology of fiber-reinforced polymeric composites than are observable using any other available microscopy techniques. This chapter describes the various aspects relating to the selection and preparation of ultrathin-section specimens of fiber-reinforced polymeric composites for examination by transmitted-light microscopy techniques. The preparation steps covered are a selection of the rough section, preparation of the rough section for preliminary mounting, grinding and polishing the primary-mount first surface, mounting the first surface on a glass slide, and preparing the second surface (top surface). The optimization of microscope conditions and analysis of specimens by microscopy techniques are also covered. In addition, examples of composite ultrathin sections that are analyzed using transmitted-light microscopy contrast methods are shown throughout.

The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.

This chapter discusses the tools and techniques of light microscopy and how they are used in the study of materials. It reviews the basic physics of light, the inner workings of light microscopes, and the relationship between resolution and depth of field. It explains the difference between amplitude and optical-phase features and how they are revealed using appropriate illumination methods. It compares images obtained using bright field and dark field illumination, polarized and cross-polarized light, and interference-contrast techniques. It also discusses the use of photometers, provides best practices and recommendations for photographing structures and features of interest, and describes the capabilities of hot-stage and hot-cell microscopes.

This article presents methods that enable one to consistently, uniformly and quickly remove substrate silicon from units without imparting damage to the structure of interest. It provides examples of electron beam probing and backside nano-probing techniques. The electron beam probing techniques are E-beam Logic State Imaging, Electron-beam Signal Image Mapping, and E-beam Device Perturbation. Backside nano-probing techniques discussed include: Electron Beam Absorbed Current, Electron Beam Induced Resistance Change, four terminal resistance measurements, resistive gate defect identification, and circuit editing. The article also presents methods to prepare electron beam probing samples where some remaining silicon is required for the transistor functions and transmission electron microscope samples from units where the substrate silicon has been partially or completely removed.