Scanning Probe Microscope (SPM) has an increasing important role in the development of nanoscale semiconductor technologies. This article presents a detailed discussion on various SPM techniques including Atomic Force Microscopy (AFM), Scanning Kelvin Probe Microscopy, Scanning Capacitance Microscopy, Scanning Spreading Resistance Microscopy, Conductive-AFM, Magnetic Force Microscopy, Scanning Surface Photo Voltage Microscopy, and Scanning Microwave Impedance Microscopy. An overview of each SPM technique is given along with examples of how each is used in the development of novel technologies, the monitoring of manufacturing processes, and the failure analysis of nanoscale semiconductor devices.

Cold spray coatings technology has the potential to provide surface enhancement for applications in sectors such as defense and aerospace, oil and gas, power generation, medical, automotive, electronics, and railways. The ability to deposit clean metallic coatings is used in applications requiring corrosion/oxidation protection, erosion/wear protection, additive manufacturing, and fabricating free forms. This chapter discusses the function, advantages, and benefits of some of these applications.

This chapter describes three approaches for 3D hot-spot localization of thermally active defects by lock-in thermography (LIT). In the first section, phase-shift analysis for analyzing stacked die packages is performed. The second example employs defocusing sequences for the localization of resistive electrical shorts in 3D architectures, and the third operates in cross sectional LIT mode to investigate defects in the insulation liner of Through Silicon Vias. All three approaches allow for a precise localization of thermally active defects in all three spatial dimensions to guide subsequent high-resolution physical analyses.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

Thermal barrier coatings (TBCs) are applied using thermal spray coating (TSC) processes to components that are internally cooled and operated in a heated environment. The TSC microstructures are prone to interactions with common metallographic procedures that may result in artifacts and misinterpretation of the TSC microstructure. This article aims to aid in identifying metallographic TSC artifacts, specifically in the air plasma spray zirconia-based TBC, including both of its common constituents, the bond coating and the top coating. Artifacts that result from specific sectioning and mounting practices, as well as from different polishing times, are presented. Additionally, the article discusses the factors in optical microscopy and scanning electron microscopy that affect microstructure interpretation.

Passive components can be broadly divided into capacitors, resistors, and inductors. Failure analysis of these components helps determine the root cause and improve the overall quality and reliability of the electronic systems. This article describes different failure analysis approaches used for these components. It discusses different types of capacitors along with their constructions and failure modes. The types include tantalum, aluminum electrolytic, multi-layered ceramics, film, and super capacitors. The article then provides a discussion on the two common types of inductors, namely, common mode choke coil and surface mount powder choke coil.

Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.

This chapter reviews the development of filament winding systems and the automated processes used in state-of-the-art filament winding facilities. It first provides a description on the early stages of modern filament winding, followed by brief information on the advances of filament winding in the computer age. Then, the chapter discusses the requirements for filament winding in manufacturing oil and gas industry components and in high-volume production of sporting goods, propane tanks, and curing ovens. The chapter concludes with examples of the versatility of filament winding in producing complex parts.

Corrosion involves chemical reactions in equilibrium that that are understood through principles of thermodynamics. In practice, the rate at which corrosion reactions occur is the most important consideration. This chapter deals with corrosion kinetics, which allows engineers to to understand rates of corrosion. The discussion covers two kinetic processes, namely electrode reactions at the cathode and anode and conduction of ions in the electrolyte. The chapter also provides information on passivation and its effect on polarization diagrams.

Moore's Law has driven many degree circuit features below the resolving capability of optical microscopy. Yet the optical microscope remains a valuable tool in failure analysis. This article describes the physics governing resolution and useful techniques for extracting the small details. It begins with the basic microscope column and construction. The article discusses microscope adjustments, brightfield and darkfield illumination, and microscope concepts important to liquid crystal techniques. It also discusses solid immersion lenses, infrared and ultraviolet microscopy and concludes with laser microscopy techniques such as thermal induced voltage alteration and external induced voltage alteration.

This article describes the basic approaches to improving the fire resistance of a polymeric material, considers the burning process on a microscale and macroscale, and discusses various test methods for determining the flammability characteristics of polymeric materials. Test methods are classified in two ways: by fire response characteristics and by particular applications of polymeric materials.

This chapter describes joining by forming processes including riveting, clinching, crimping, and dieless joining techniques. It also discusses the fatigue behavior of clinched joints and the results of fatigue tests that compare clinched and spot welded joints.

The ultimate goal of the failure analysis process is to find physical evidence that can identify the root cause of the failure. Transmission electron microscopy (TEM) has emerged as a powerful tool to characterize subtle defects. This article discusses the sample preparation procedures based on focused ion beam milling used for TEM sample preparation. It describes the principles behind commonly used imaging modes in semiconductor failure analysis and how these operation modes can be utilized to selectively maximize signal from specific beam-specimen interactions to generate useful information about the defect. Various elemental analysis techniques, namely energy dispersive spectroscopy, electron energy loss spectroscopy, and energy-filtered TEM, are described using examples encountered in failure analysis. The origin of different image contrast mechanisms, their interpretation, and analytical techniques for composition analysis are discussed. The article also provides information on the use of off-axis electron holography technique in failure analysis.

Cross-sectioning is a technique used for process development and reverse engineering. This article introduces novice analysts to the methods of cross-sectioning semiconductor devices and provides a refresher for the more experienced analysts. Topics covered include encapsulated (potted) device sectioning techniques, non-encapsulated device techniques, utilization of the focused ion beam (FIB) making a cross-section and/or enhancing a physically polished one. Delineation methods for revealing structures are also discussed. These can be chemical etchants, chemo-mechanical polishing, and ion milling, either in the FIB or in a dedicated ion mill.

The management of a failure analysis (FA) laboratory requires a broad range of activities to optimize the efficiency of the operation. The purpose of this article is to stimulate readers to consider the various aspects of FA laboratory operations and their respective business management requirements. The various aspects include: staffing, laboratory organization, lab design and operations, strategic development, financial management, and metrics and measurements. References for further reading and examples of resource materials are also included.

This article reviews the basic physics behind active photon injection for local photocurrent generation in silicon and thermal laser stimulation along with standard scanning optical microscopy failure analysis tools. The discussion includes several models for understanding the local thermal effects on metallic lines, junctions, and complete devices. The article also provides a description and case study examples of multiple photocurrent and thermal injection techniques. The photocurrent examples are based on Optical Beam-Induced Current and Light-Induced Voltage Alteration. The thermal stimulus examples are Optical Beam-Induced Resistance Change/Thermally-Induced Voltage Alteration and Seebeck Effect Imaging. Lastly, the article discusses the application of solid immersion lenses to improve spatial resolution.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

This chapter presents an overview of microprocessor and application specific integrated circuit (IC) testing. It begins with a description of key industry trends that will impact how ICs will be tested in the future. Next, it provides a brief description of the most common tests applied in the IC industry, where technical issues that are causing methodology changes are emphasized. These include functional testing, structural testing, scan-based delay testing, built-in self-testing, memory testing, analog circuit testing, system-on-a-chip testing, and reliability testing. Trends discussed have driven the development of novel focus areas in test and the chapter discusses several of those areas, including test data volume containment, test power containment, and novel methods of defect-based test.

This article describes the most common, general-purpose analog design-for-test (DFT) methods, analog test buses and loopback, and shows their advantages and limitations in diagnosability and automatability. It also describes DFT and built-in self-test (BIST) techniques for the most common analog functions, namely phase-locked loop, serializer-deserializer, analog/digital converters, and radio frequency. Lastly, the challenges of creating BIST for analog functions are summarized, along with seven principles that must be exploited to meet these challenges. These principles show how the design constraints for analog BIST circuitry can be more relaxed than for the circuit under test, while delivering the required test accuracy and speed.

In the Semiconductor I/C industry, it has been well documented that the proportion of factory and customer field returns attributed to device damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40 to 50%. This study entailed EOS and ESD simulation using a variety of models, namely the Human Body Model (HBM), the Charged Device Model (CDM) and the so-called Machine Model (MM), and then conducting electrical and physical failure analysis and comparing the results with documented analyses performed on customer field returns and factory failures. It is shown that a distinction can be made between EOS and ESD failures and between the characteristic failure signatures produced by the ESD models. The CDM physical failure location is at the input buffer and in the gate oxide, where as both HBM and MM failures occur mostly in the contacts at the input protection structures.