Cross-sectioning refers to the process of exposing the internal layers and printed devices below the surface by cleaving through the wafer. This article discusses in detail the steps involved in common cross-sectioning methods. These include sample preparation, scribing, indenting, and cleaving. The article also provides information on options for mounting, handling, and cleaning of samples during and after the cleaving process. The general procedures, tools required, and considerations that need to be taken into account to perform these techniques are considered.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

Induction heating has found widespread use as a method to raise the temperature of a metal prior to forming or joining, or to change its metallurgical structure. However, induction heating has specialized capabilities that make it suitable for applications outside of metal treatment and fabrication. This chapter summarizes some of the special applications of induction heating, including those in the plastics, packaging, electronics, glass, chemical, and metal-finishing industries. The chapter concludes with a discussion of the application of induction heating for vacuum processes.

This chapter describes three approaches for 3D hot-spot localization of thermally active defects by lock-in thermography (LIT). In the first section, phase-shift analysis for analyzing stacked die packages is performed. The second example employs defocusing sequences for the localization of resistive electrical shorts in 3D architectures, and the third operates in cross sectional LIT mode to investigate defects in the insulation liner of Through Silicon Vias. All three approaches allow for a precise localization of thermally active defects in all three spatial dimensions to guide subsequent high-resolution physical analyses.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.

Transistors are the most important active structure of any semiconductor component. Performance characteristics of such devices within the specifications are key to ensuring proper functionality and long-term reliability of the product. In this article, a summary of the semiconductor technology from design to manufacturing and the characterization methods are discussed. The focus is on two prominent MOS structures: planar MOS device and FinFET device. The article covers the device parameters and device properties that determine the design criteria and the device tuning procedures. The discussion includes the effects of drain induced barrier lowering, velocity saturation, hot carrier degradation, and short channel on these devices.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

The most common methods for preparing polymeric composites for microscopic analysis can be used for most fiber-reinforced composite materials. There are, however, a few composite materials that require special preparation techniques. This chapter discusses the processes involved in the preparation of titanium honeycomb composites, boron fiber composites, titanium/polymeric composite hybrids, and uncured prepreg materials.

Several specialized instruments are available for the metallographer to use as tools to gather key information on the characteristics of the microstructure being analyzed. These include microscopes that use electrons as a source of illumination instead of light and x-ray diffraction equipment. This chapter describes how these instruments can be used to gather important information about a microstructure. The instruments covered include image analyzers, transmission electron microscopes, scanning electron microscopes, electron probe microanalyzers, scanning transmission electron microscopes, x-ray diffractometers, microhardness testers, and hot microhardness testers. A list of other instruments that are usually located in a research laboratory or specialized testing laboratory is also provided.

The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.

This article addresses the ancillary issues regarding the nanoprobing and characterization of transistors, probing copper metallization layers, and the various imaging techniques. The discussion includes several characterization examples of known transistor failure types, namely four probe transistor characterization, two probe transistor characterization, and probing and characterizing metallization issues. The imaging techniques discussed are those that are specific to atomic force nanoprober or scanning electron microscope based tools. They are current contrast imaging, scanning capacitance imaging, e-beam absorbed current imaging, e-beam induced current imaging, e-beam induced resistance change imaging, and active voltage contrast imaging.

Cross-sectioning is a technique used for process development and reverse engineering. This article introduces novice analysts to the methods of cross-sectioning semiconductor devices and provides a refresher for the more experienced analysts. Topics covered include encapsulated (potted) device sectioning techniques, non-encapsulated device techniques, utilization of the focused ion beam (FIB) making a cross-section and/or enhancing a physically polished one. Delineation methods for revealing structures are also discussed. These can be chemical etchants, chemo-mechanical polishing, and ion milling, either in the FIB or in a dedicated ion mill.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

The ultimate goal of the failure analysis process is to find physical evidence that can identify the root cause of the failure. Transmission electron microscopy (TEM) has emerged as a powerful tool to characterize subtle defects. This article discusses the sample preparation procedures based on focused ion beam milling used for TEM sample preparation. It describes the principles behind commonly used imaging modes in semiconductor failure analysis and how these operation modes can be utilized to selectively maximize signal from specific beam-specimen interactions to generate useful information about the defect. Various elemental analysis techniques, namely energy dispersive spectroscopy, electron energy loss spectroscopy, and energy-filtered TEM, are described using examples encountered in failure analysis. The origin of different image contrast mechanisms, their interpretation, and analytical techniques for composition analysis are discussed. The article also provides information on the use of off-axis electron holography technique in failure analysis.

The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.

This chapter provides a comprehensive overview over all phenomena related to Voltage Contrast (VC) mechanisms in SEM and FIB. The multiple advantages, possibilities, and limits of active and passive VC failure localization are systemized and discussed. The knowledge of all facts influencing the VC generation (capacitance, leakage, doping, and circuitry) is very helpful for successful failure localization.

This chapter surveys both basic quality and basic reliability concepts as an introduction to the failure analysis professional. It begins with a section describing the distinction between quality and reliability and moves on to provide an overview of the concept of experiment design along with an example. The chapter then discusses the purposes of reliability engineering and introduces four basic statistical distribution functions useful in reliability engineering, namely normal, lognormal, exponential, and Weibull. It also provides information on three fundamental acceleration models used by reliability engineers: Arrhenius, Eyring, and power law models. The chapter concludes with information on failure rates and mechanisms and the two techniques for uncovering reliability issues, namely burn-in and outlier screening.