Cross-sectioning refers to the process of exposing the internal layers and printed devices below the surface by cleaving through the wafer. This article discusses in detail the steps involved in common cross-sectioning methods. These include sample preparation, scribing, indenting, and cleaving. The article also provides information on options for mounting, handling, and cleaning of samples during and after the cleaving process. The general procedures, tools required, and considerations that need to be taken into account to perform these techniques are considered.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

This chapter summarizes critical gaps and long-term needs in failure analysis technology as it relates to logic and memory devices and IC packages. It assesses the impact of vertical integration, new materials, and expansion in the third dimension on volume analysis, sample preparation and measurement methods, and cross-sectioning and imaging.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

Transistors are the most important active structure of any semiconductor component. Performance characteristics of such devices within the specifications are key to ensuring proper functionality and long-term reliability of the product. In this article, a summary of the semiconductor technology from design to manufacturing and the characterization methods are discussed. The focus is on two prominent MOS structures: planar MOS device and FinFET device. The article covers the device parameters and device properties that determine the design criteria and the device tuning procedures. The discussion includes the effects of drain induced barrier lowering, velocity saturation, hot carrier degradation, and short channel on these devices.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

This chapter surveys both basic quality and basic reliability concepts as an introduction to the failure analysis professional. It begins with a section describing the distinction between quality and reliability and moves on to provide an overview of the concept of experiment design along with an example. The chapter then discusses the purposes of reliability engineering and introduces four basic statistical distribution functions useful in reliability engineering, namely normal, lognormal, exponential, and Weibull. It also provides information on three fundamental acceleration models used by reliability engineers: Arrhenius, Eyring, and power law models. The chapter concludes with information on failure rates and mechanisms and the two techniques for uncovering reliability issues, namely burn-in and outlier screening.

Induction heating has found widespread use as a method to raise the temperature of a metal prior to forming or joining, or to change its metallurgical structure. However, induction heating has specialized capabilities that make it suitable for applications outside of metal treatment and fabrication. This chapter summarizes some of the special applications of induction heating, including those in the plastics, packaging, electronics, glass, chemical, and metal-finishing industries. The chapter concludes with a discussion of the application of induction heating for vacuum processes.

Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

Education and training play an important role if the failure analyst is to be successful in his or her work. This article discusses the history of training activities in the failure/product analysis discipline and describes where this area is heading. It provides information on three areas of education and training that should be given to the analyst for him or her to be successful developing and fielding modern semiconductor components: analysis process, technology, and technique training.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

This chapter presents an overview of microprocessor and application specific integrated circuit (IC) testing. It begins with a description of key industry trends that will impact how ICs will be tested in the future. Next, it provides a brief description of the most common tests applied in the IC industry, where technical issues that are causing methodology changes are emphasized. These include functional testing, structural testing, scan-based delay testing, built-in self-testing, memory testing, analog circuit testing, system-on-a-chip testing, and reliability testing. Trends discussed have driven the development of novel focus areas in test and the chapter discusses several of those areas, including test data volume containment, test power containment, and novel methods of defect-based test.

The ultimate goal of the failure analysis process is to find physical evidence that can identify the root cause of the failure. Transmission electron microscopy (TEM) has emerged as a powerful tool to characterize subtle defects. This article discusses the sample preparation procedures based on focused ion beam milling used for TEM sample preparation. It describes the principles behind commonly used imaging modes in semiconductor failure analysis and how these operation modes can be utilized to selectively maximize signal from specific beam-specimen interactions to generate useful information about the defect. Various elemental analysis techniques, namely energy dispersive spectroscopy, electron energy loss spectroscopy, and energy-filtered TEM, are described using examples encountered in failure analysis. The origin of different image contrast mechanisms, their interpretation, and analytical techniques for composition analysis are discussed. The article also provides information on the use of off-axis electron holography technique in failure analysis.

Scanning Probe Microscope (SPM) has an increasing important role in the development of nanoscale semiconductor technologies. This article presents a detailed discussion on various SPM techniques including Atomic Force Microscopy (AFM), Scanning Kelvin Probe Microscopy, Scanning Capacitance Microscopy, Scanning Spreading Resistance Microscopy, Conductive-AFM, Magnetic Force Microscopy, Scanning Surface Photo Voltage Microscopy, and Scanning Microwave Impedance Microscopy. An overview of each SPM technique is given along with examples of how each is used in the development of novel technologies, the monitoring of manufacturing processes, and the failure analysis of nanoscale semiconductor devices.

A typical mobile processor die may contain, among other things, a variety of high-performance as well as low-power processing cores along with 5G modems, Wi-Fi modules, image processors, GPUs, and security modules, with a total transistor count exceeding 10 billion. Such designs pose many challenges for yield ramp and diagnostics. This chapter examines these challenges and the growing demand for innovative solutions to help failure analysts quickly and accurately isolate faults. It also assesses the capabilities and future potential of ATPG scan diagnostics, streaming scan networks, and advanced fault models for diagnosing embedded memory.

Cross-sectioning is a technique used for process development and reverse engineering. This article introduces novice analysts to the methods of cross-sectioning semiconductor devices and provides a refresher for the more experienced analysts. Topics covered include encapsulated (potted) device sectioning techniques, non-encapsulated device techniques, utilization of the focused ion beam (FIB) making a cross-section and/or enhancing a physically polished one. Delineation methods for revealing structures are also discussed. These can be chemical etchants, chemo-mechanical polishing, and ion milling, either in the FIB or in a dedicated ion mill.

The management of a failure analysis (FA) laboratory requires a broad range of activities to optimize the efficiency of the operation. The purpose of this article is to stimulate readers to consider the various aspects of FA laboratory operations and their respective business management requirements. The various aspects include: staffing, laboratory organization, lab design and operations, strategic development, financial management, and metrics and measurements. References for further reading and examples of resource materials are also included.