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Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110067
EISBN: 978-1-62708-247-1
... signature analysis and GHz-SAM. GHz -SAM integrated circuit inspection scanning acoustic microscope semiconductor packages spectral signature analysis Introduction The Scanning Acoustic Microscope (SAM) has been adopted by assembly and test facilities, packaging researchers and integrated...
Abstract
The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.
Image
in Non-destructive Techniques for Advanced Board Level Failure Analysis
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110010
EISBN: 978-1-62708-247-1
... Abstract As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes...
Abstract
As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110025
EISBN: 978-1-62708-247-1
... acoustic microscopy time-domain-reflectometry X-ray microscopy Following ongoing trends of miniaturization and increased functionality, printed circuit boards (PCB) have to cope with increased solder joint densities, smaller feature sizes and an adaption to a larger variety of semiconductor package...
Abstract
In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110262
EISBN: 978-1-62708-247-1
... (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best...
Abstract
Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110673
EISBN: 978-1-62708-247-1
... of semiconductor technology (design, process, test, packaging, reliability, etc.) Understands the information a tool or technique can yield Can operate a variety of analysis tools I have ordered the list in the order of importance for training. The top items on this list are things that are unchanging...
Abstract
Education and training play an important role if the failure analyst is to be successful in his or her work. This article discusses the history of training activities in the failure/product analysis discipline and describes where this area is heading. It provides information on three areas of education and training that should be given to the analyst for him or her to be successful developing and fielding modern semiconductor components: analysis process, technology, and technique training.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110062
EISBN: 978-1-62708-247-1
... of semiconductor packaging structures have prompted X-ray equipment manufacturers to significantly improve the 3D micro-CT imaging capability [11 , 12] . Most X-ray equipment manufacturers now provide 3D models with fully automated data acquisition, reconstruction, and data analysis packages. In a typical 3D...
Abstract
X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110132
EISBN: 978-1-62708-247-1
... review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly...
Abstract
Time-domain based characterization methods, mainly time-domain reflectometry (TDR) and time-domain transmissometry (TDT), have been used to locate faults in twisted cables, telegraph lines, and connectors in the electrical and telecommunication industry. This article provides a brief review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly made it a well-adopted tool in the industry. The third part of this article introduces a new method which combines impulse signal and the TDT concept, and discusses a combo TDR and TDT method. Cases studies and application notes are shared and discussed for each technique. Application benefits and limitations of these techniques (TDR, EOTPR, and combo TDR/TDT) are summarized and compared.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110550
EISBN: 978-1-62708-247-1
... Abstract The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support...
Abstract
The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110563
EISBN: 978-1-62708-247-1
... Abstract This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies...
Abstract
This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110144
EISBN: 978-1-62708-247-1
... techniques ”, Microelectronic Failure Analysis, Desk Reference , 5th Edition • Parañal P.E.B. , “ Localized die metallization damage induced during laser-marking of a semiconductor package ”, Proc 33rd Int'l Symp for Testing and Failure Analysis , San Jose, CA , November 2007 , pp. 226...
Abstract
The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110524
EISBN: 978-1-62708-247-1
... to be more obvious (e.g., contact corrosion or packaging-induced failures). Types of Semiconductor Laser Active Regions It is helpful to understand that there are three types of semiconductor lasers, from the standpoint of active region degradation. The first, and ideal type, would be those that have...
Abstract
Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110391
EISBN: 978-1-62708-247-1
... materials along one of its cleavage planes. Semiconductor wafers and bare dice can be cleaved but packaged devices cannot. Packages contain amorphous materials (such as metals and epoxies) that do not have cleavage planes. The deformation of these materials interferes with other materials’ cleavages...
Abstract
Cross-sectioning is a technique used for process development and reverse engineering. This article introduces novice analysts to the methods of cross-sectioning semiconductor devices and provides a refresher for the more experienced analysts. Topics covered include encapsulated (potted) device sectioning techniques, non-encapsulated device techniques, utilization of the focused ion beam (FIB) making a cross-section and/or enhancing a physically polished one. Delineation methods for revealing structures are also discussed. These can be chemical etchants, chemo-mechanical polishing, and ion milling, either in the FIB or in a dedicated ion mill.
Book Chapter
Series: ASM Technical Books
Publisher: ASM International
Published: 01 June 1988
DOI: 10.31399/asm.tb.eihdca.t65220281
EISBN: 978-1-62708-341-6
... and fabrication. This chapter summarizes some of the special applications of induction heating, including those in the plastics, packaging, electronics, glass, chemical, and metal-finishing industries. The chapter concludes with a discussion of the application of induction heating for vacuum processes...
Abstract
Induction heating has found widespread use as a method to raise the temperature of a metal prior to forming or joining, or to change its metallurgical structure. However, induction heating has specialized capabilities that make it suitable for applications outside of metal treatment and fabrication. This chapter summarizes some of the special applications of induction heating, including those in the plastics, packaging, electronics, glass, chemical, and metal-finishing industries. The chapter concludes with a discussion of the application of induction heating for vacuum processes.
Book Chapter
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110447
EISBN: 978-1-62708-247-1
... package (QFP) device parts ( Figure 1 ). The result is that with one AES measurement the solder quality assessment of the product can be made. Figure 1 Examples of QFPs (top) and BGAs (bottom) Every year semiconductor devices that are deemed obsolete or unusable are sent to recycling centers...
Abstract
There are several analytical methods available that can be used in-line on whole wafers as well as off-line on de-processed products that are returned from the field. These techniques are surface analytical techniques that can be used to characterize the bulk of the material. The main six methods used in semiconductor industry are: Auger spectroscopy, dynamic secondary ion mass spectroscopy, time of flight static secondary ion mass spectroscopy (ToF-SIMS), X-ray photoelectron spectroscopy, scanning electron microscope-energy dispersive X-ray spectroscopy (SEM-EDX), and transmission electron microscope-EDX. This review specifically addresses ToF-SIMS and describes some typical examples of the application of Auger and SEM-EDX.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110634
EISBN: 978-1-62708-247-1
... on the capital cost of automatic test equipment (ATE) and the increased test times. Despite these trends toward greater complexity, semiconductor market forces are trying to drive down testing costs and to shrink the time between product introductions. Meanwhile, the manufacturing cost per transistor...
Abstract
This chapter presents an overview of microprocessor and application specific integrated circuit (IC) testing. It begins with a description of key industry trends that will impact how ICs will be tested in the future. Next, it provides a brief description of the most common tests applied in the IC industry, where technical issues that are causing methodology changes are emphasized. These include functional testing, structural testing, scan-based delay testing, built-in self-testing, memory testing, analog circuit testing, system-on-a-chip testing, and reliability testing. Trends discussed have driven the development of novel focus areas in test and the chapter discusses several of those areas, including test data volume containment, test power containment, and novel methods of defect-based test.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110666
EISBN: 978-1-62708-247-1
... that have escaped final test, where “reliability defects” may manifest themselves over time as reliability fails. In fact, quality and reliability defect-driven measures of a group of semiconductor devices have been shown to be closely related to one another, with a high correlation between initial...
Abstract
This chapter surveys both basic quality and basic reliability concepts as an introduction to the failure analysis professional. It begins with a section describing the distinction between quality and reliability and moves on to provide an overview of the concept of experiment design along with an example. The chapter then discusses the purposes of reliability engineering and introduces four basic statistical distribution functions useful in reliability engineering, namely normal, lognormal, exponential, and Weibull. It also provides information on three fundamental acceleration models used by reliability engineers: Arrhenius, Eyring, and power law models. The chapter concludes with information on failure rates and mechanisms and the two techniques for uncovering reliability issues, namely burn-in and outlier screening.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110153
EISBN: 978-1-62708-247-1
... combinations of modules, packages, die sizes, and material compositions combining metal alloys, epoxy with fillers, glass, die attach, glass fibers, ceramic, silicone and so on. This is further complicated by Coefficient of Thermal Expansion (CTE) mismatch of the layers and the need to polish dissimilar...
Abstract
The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.
Book: Principles of Soldering
Series: ASM Technical Books
Publisher: ASM International
Published: 01 April 2004
DOI: 10.31399/asm.tb.ps.t62440145
EISBN: 978-1-62708-352-2
.... , 2001 . Void-Free, Flux-Free Solder: A Method of Soldering, U.K. Patent 0104577.2 • Mackay C.A. and Levine S.W. , 1986 . Solder Sealing Semiconductor Packages , IEEE Trans. Components Hybrids Manuf. Technol. , Vol 9 (No. 2 ), p 195 – 201 10.1109/TCHMT.1986.1136636...
Abstract
This chapter considers the materials and processing aspects of soldering and the manner in which these interrelate in the development of joining processes. It discusses the processes involved in eliminating or suppressing metallurgical and mechanical constraints as well as constraints imposed by the components.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110279
EISBN: 978-1-62708-247-1
... Abstract Transistors are the most important active structure of any semiconductor component. Performance characteristics of such devices within the specifications are key to ensuring proper functionality and long-term reliability of the product. In this article, a summary of the semiconductor...
Abstract
Transistors are the most important active structure of any semiconductor component. Performance characteristics of such devices within the specifications are key to ensuring proper functionality and long-term reliability of the product. In this article, a summary of the semiconductor technology from design to manufacturing and the characterization methods are discussed. The focus is on two prominent MOS structures: planar MOS device and FinFET device. The article covers the device parameters and device properties that determine the design criteria and the device tuning procedures. The discussion includes the effects of drain induced barrier lowering, velocity saturation, hot carrier degradation, and short channel on these devices.