Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.

Education and training play an important role if the failure analyst is to be successful in his or her work. This article discusses the history of training activities in the failure/product analysis discipline and describes where this area is heading. It provides information on three areas of education and training that should be given to the analyst for him or her to be successful developing and fielding modern semiconductor components: analysis process, technology, and technique training.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

Transistors are the most important active structure of any semiconductor component. Performance characteristics of such devices within the specifications are key to ensuring proper functionality and long-term reliability of the product. In this article, a summary of the semiconductor technology from design to manufacturing and the characterization methods are discussed. The focus is on two prominent MOS structures: planar MOS device and FinFET device. The article covers the device parameters and device properties that determine the design criteria and the device tuning procedures. The discussion includes the effects of drain induced barrier lowering, velocity saturation, hot carrier degradation, and short channel on these devices.

Photon emission (PE) is one of the major optical techniques for contactless isolation of functional faults in integrated circuits (ICs) in full electrical operation. This article describes the fundamental mechanisms of PE in silicon based ICs. It presents the opportunities of contactless characterization for the most important electronic device, the MOS - Field Effect Transistor, the heart of ICs and their basic digital element, the CMOS inverter. The article discusses the specification and selection of detectors for proper PE applications. The main topics are image resolution, sensitivity, and spectral range of the detectors. The article also discusses the value and application of spectral information in the PE signal. It describes state of the art IC technologies. Finally, the article discusses the applications of PE in ICs and also I/O devices, integrated bipolar transistors in BiCMOS technologies, and parasitic bipolar effects like latch up.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.

This chapter presents an overview of microprocessor and application specific integrated circuit (IC) testing. It begins with a description of key industry trends that will impact how ICs will be tested in the future. Next, it provides a brief description of the most common tests applied in the IC industry, where technical issues that are causing methodology changes are emphasized. These include functional testing, structural testing, scan-based delay testing, built-in self-testing, memory testing, analog circuit testing, system-on-a-chip testing, and reliability testing. Trends discussed have driven the development of novel focus areas in test and the chapter discusses several of those areas, including test data volume containment, test power containment, and novel methods of defect-based test.

This chapter presents the theory and practice associated with the application of thin films. The first half of the chapter describes physical deposition processes in which functional coatings are deposited on component surfaces using mechanical, electromechanical, or thermodynamic techniques. Physical vapor deposition (PVD) techniques include sputtering, e-beam evaporation, arc-PVD, and ion plating and are best suited for elements and compounds with moderate melting points or when a high-purity film is required. The remainder of the chapter covers chemical vapor deposition (CVD) processes, including atomic layer deposition, plasma-enhanced and plasma-assisted CVD, and various forms of vapor-phase epitaxy, which are commonly used for compound films or when deposit purity is less critical. A brief application overview is also presented.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

This chapter describes the processes, applications, and limitations of forming and shaping various materials. It discusses bulk forming, hot working, cold working, sheet forming, and polymer and powder processing.

Many defects generate excessive heat during operation; this is due to the power dissipation associated with the excess current flow at the defect site. There are several thermal detection techniques for failure analysis and this article focuses on infrared thermography with lock-in detection, which detects an object's temperature from its infrared emission based on blackbody radiation physics. The basic principles and the interpretation of the results are reviewed. Some typical results and a series of examples illustrating the application of this technique are also shown. Brief sections are devoted to the discussion on liquid-crystal imaging and fluorescent microthermal imaging technique for thermal detection.

Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.

Laser Voltage Probing (LVP) is a key enabling technology that has matured into a well-established and essential analytical optical technique that is crucial for observing and evaluating internal circuit activity. This article begins by providing an overview on LVP history and LVP theory, providing information on electro-optical effects and free-carrier effects. It then focuses on commercially available continuous wave LVP systems. Alternative optoelectronic imaging and probing technologies for fault isolation, namely frequency mapping and laser voltage tracing, are also discussed. The subsequent section provides information on the use of Visible Laser Probing. The article closes with some common LVP observations/considerations and limitations and future work concerning LVP.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.