This article presents best practices for the metallographic preparation of specimens produced via thermal spray coating methods. It outlines typical metallographic preparation process flow, highlighting important considerations for obtaining a clear and representative specimen suitable for characterization via examination techniques, such as optical or electron microscopy. The process flow includes preliminary resin infiltration, sectioning, mounting, grinding, and polishing. To aid in the identification and resolution of common issues during subsequent specimen analysis, the article presents common issues, along with causes and mitigation strategies. It describes the processes involved in the interpretation of the thermal spray coating microstructure.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

This chapter provides a comprehensive overview over all phenomena related to Voltage Contrast (VC) mechanisms in SEM and FIB. The multiple advantages, possibilities, and limits of active and passive VC failure localization are systemized and discussed. The knowledge of all facts influencing the VC generation (capacitance, leakage, doping, and circuitry) is very helpful for successful failure localization.

This article addresses the ancillary issues regarding the nanoprobing and characterization of transistors, probing copper metallization layers, and the various imaging techniques. The discussion includes several characterization examples of known transistor failure types, namely four probe transistor characterization, two probe transistor characterization, and probing and characterizing metallization issues. The imaging techniques discussed are those that are specific to atomic force nanoprober or scanning electron microscope based tools. They are current contrast imaging, scanning capacitance imaging, e-beam absorbed current imaging, e-beam induced current imaging, e-beam induced resistance change imaging, and active voltage contrast imaging.

This article presents methods that enable one to consistently, uniformly and quickly remove substrate silicon from units without imparting damage to the structure of interest. It provides examples of electron beam probing and backside nano-probing techniques. The electron beam probing techniques are E-beam Logic State Imaging, Electron-beam Signal Image Mapping, and E-beam Device Perturbation. Backside nano-probing techniques discussed include: Electron Beam Absorbed Current, Electron Beam Induced Resistance Change, four terminal resistance measurements, resistive gate defect identification, and circuit editing. The article also presents methods to prepare electron beam probing samples where some remaining silicon is required for the transistor functions and transmission electron microscope samples from units where the substrate silicon has been partially or completely removed.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

This chapter details low-temperature test procedures and equipment. It discusses the role temperature plays in the properties of typical engineering materials. The effect that lowering the temperature of a solid has on the mechanical properties of a material is summarized for three principal groups of engineering materials: metals, ceramics, and polymers (including fiber-reinforced polymers). The chapter describes the factors that influence the selection of tensile testing procedures for low-temperature evaluation, along with a comparison of tensile and compression tests. It covers the parameters and standards related to low-temperature tensile testing. The chapter discusses the factors involved in controlling test temperature. Finally, the chapter discusses the safety issues concerning the use of cooled methanol, liquid-nitrogen, and liquid helium.

Root cause of failure in automotive electronics cannot be explained by the failure signatures of failed devices. Deeper investigations in these cases reveals that a superimposition of impact factors, which can never be represented by usual qualification testing, caused the failure. This article highlights some of the most frequent early life failure types in automotive applications. It describes some of the critical things to be considered while handling packages and printed circuit board layout. The article also provides information on failure anamnesis that shows how to use history, failure signatures, environmental conditions, regional failure occurrences, user profile issues, and more in the failure analysis process to improve root cause findings.

This appendix provides information on organizations that issue specifications and standards related to titanium and its alloys.

The ultimate goal of the failure analysis process is to find physical evidence that can identify the root cause of the failure. Transmission electron microscopy (TEM) has emerged as a powerful tool to characterize subtle defects. This article discusses the sample preparation procedures based on focused ion beam milling used for TEM sample preparation. It describes the principles behind commonly used imaging modes in semiconductor failure analysis and how these operation modes can be utilized to selectively maximize signal from specific beam-specimen interactions to generate useful information about the defect. Various elemental analysis techniques, namely energy dispersive spectroscopy, electron energy loss spectroscopy, and energy-filtered TEM, are described using examples encountered in failure analysis. The origin of different image contrast mechanisms, their interpretation, and analytical techniques for composition analysis are discussed. The article also provides information on the use of off-axis electron holography technique in failure analysis.

Cross-sectioning refers to the process of exposing the internal layers and printed devices below the surface by cleaving through the wafer. This article discusses in detail the steps involved in common cross-sectioning methods. These include sample preparation, scribing, indenting, and cleaving. The article also provides information on options for mounting, handling, and cleaning of samples during and after the cleaving process. The general procedures, tools required, and considerations that need to be taken into account to perform these techniques are considered.

This article provides an introduction to the dynamic random access memory (DRAM) operation with a focus to localization techniques of the defects combined with some physical failure analysis examples and case studies for memory array failures. It discusses the electrical measurement techniques for array failure analysis. The article then presents know-how-based analysis techniques of array failures by bitmap classification. The limits of bitmapping that lead to well-known localization techniques like thermally induced voltage alteration and optical beam induced resistance change are also discussed. The article concludes by providing information on soft defect localization techniques.

Many defects generate excessive heat during operation; this is due to the power dissipation associated with the excess current flow at the defect site. There are several thermal detection techniques for failure analysis and this article focuses on infrared thermography with lock-in detection, which detects an object's temperature from its infrared emission based on blackbody radiation physics. The basic principles and the interpretation of the results are reviewed. Some typical results and a series of examples illustrating the application of this technique are also shown. Brief sections are devoted to the discussion on liquid-crystal imaging and fluorescent microthermal imaging technique for thermal detection.

The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

There are several analytical methods available that can be used in-line on whole wafers as well as off-line on de-processed products that are returned from the field. These techniques are surface analytical techniques that can be used to characterize the bulk of the material. The main six methods used in semiconductor industry are: Auger spectroscopy, dynamic secondary ion mass spectroscopy, time of flight static secondary ion mass spectroscopy (ToF-SIMS), X-ray photoelectron spectroscopy, scanning electron microscope-energy dispersive X-ray spectroscopy (SEM-EDX), and transmission electron microscope-EDX. This review specifically addresses ToF-SIMS and describes some typical examples of the application of Auger and SEM-EDX.

This chapter surveys both basic quality and basic reliability concepts as an introduction to the failure analysis professional. It begins with a section describing the distinction between quality and reliability and moves on to provide an overview of the concept of experiment design along with an example. The chapter then discusses the purposes of reliability engineering and introduces four basic statistical distribution functions useful in reliability engineering, namely normal, lognormal, exponential, and Weibull. It also provides information on three fundamental acceleration models used by reliability engineers: Arrhenius, Eyring, and power law models. The chapter concludes with information on failure rates and mechanisms and the two techniques for uncovering reliability issues, namely burn-in and outlier screening.

This chapter describes how ultrasonic testing came to be a viable method for evaluating intergranular stress-corrosion cracking (SCC) in large-diameter stainless steel pipe welds in boiling water reactor service. Intergranular SCC can be difficult to detect using nondestructive evaluation (NDE) techniques because of its treelike branching pattern and its location in the heat-affected zone within the weld. As the chapter explains, by optimizing excitation and reflected waveforms, switching to dual-element sensing, properly orienting the scanning path, and using crack-tip diffraction and amplitude-drop techniques, the height, length, and location of intergranular cracks can be accurately determined anywhere along the walls of the pipe as well as in weld areas.

This article provides an overview of the most common micro-analytical technique in the failure analysis laboratory: energy dispersive X-ray spectroscopy (EDS). It discusses the general characteristics, advantages, and disadvantages of some of the X-ray detectors attached to the scanning electron microscope chamber including the lithium-drifted EDS detector, silicon drift detector (SDD), and wavelength dispersive X-ray detector. The article then provides information on qualitative and quantitative X-ray analysis programs followed by a discussion on EDS elemental mapping. The discussion includes a comparison of scanning transmission electron microscope-EDS elemental mapping and mapping with an SDD. A brief section is devoted to the discussion on the artifacts that occur during X-ray mapping.