In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.

Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

Passive components can be broadly divided into capacitors, resistors, and inductors. Failure analysis of these components helps determine the root cause and improve the overall quality and reliability of the electronic systems. This article describes different failure analysis approaches used for these components. It discusses different types of capacitors along with their constructions and failure modes. The types include tantalum, aluminum electrolytic, multi-layered ceramics, film, and super capacitors. The article then provides a discussion on the two common types of inductors, namely, common mode choke coil and surface mount powder choke coil.

Root cause of failure in automotive electronics cannot be explained by the failure signatures of failed devices. Deeper investigations in these cases reveals that a superimposition of impact factors, which can never be represented by usual qualification testing, caused the failure. This article highlights some of the most frequent early life failure types in automotive applications. It describes some of the critical things to be considered while handling packages and printed circuit board layout. The article also provides information on failure anamnesis that shows how to use history, failure signatures, environmental conditions, regional failure occurrences, user profile issues, and more in the failure analysis process to improve root cause findings.

The ultimate goal of the failure analysis process is to find physical evidence that can identify the root cause of the failure. Transmission electron microscopy (TEM) has emerged as a powerful tool to characterize subtle defects. This article discusses the sample preparation procedures based on focused ion beam milling used for TEM sample preparation. It describes the principles behind commonly used imaging modes in semiconductor failure analysis and how these operation modes can be utilized to selectively maximize signal from specific beam-specimen interactions to generate useful information about the defect. Various elemental analysis techniques, namely energy dispersive spectroscopy, electron energy loss spectroscopy, and energy-filtered TEM, are described using examples encountered in failure analysis. The origin of different image contrast mechanisms, their interpretation, and analytical techniques for composition analysis are discussed. The article also provides information on the use of off-axis electron holography technique in failure analysis.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

Diagnosing the root cause of a failure is particularly challenging if the symptom of the failure is not consistently observable. This article focuses on Laser Assisted Device Alteration/Soft Defect Localization (LADA/SDL), a global fault isolation technique, for detecting such failures. The discussion begins with a section describing the three steps in LADA/SDL analysis setup: create the test loop with the fail flag and loop trigger, select the laser dwell time, and select the shmoo bias point. An overview of LADA/SDL workflow is then presented followed by a brief section on time-resolved LADA. The closing pages of the article consider in detail SDL laser interaction physics and LADA laser interaction physics.

The management of a failure analysis (FA) laboratory requires a broad range of activities to optimize the efficiency of the operation. The purpose of this article is to stimulate readers to consider the various aspects of FA laboratory operations and their respective business management requirements. The various aspects include: staffing, laboratory organization, lab design and operations, strategic development, financial management, and metrics and measurements. References for further reading and examples of resource materials are also included.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

There are several analytical methods available that can be used in-line on whole wafers as well as off-line on de-processed products that are returned from the field. These techniques are surface analytical techniques that can be used to characterize the bulk of the material. The main six methods used in semiconductor industry are: Auger spectroscopy, dynamic secondary ion mass spectroscopy, time of flight static secondary ion mass spectroscopy (ToF-SIMS), X-ray photoelectron spectroscopy, scanning electron microscope-energy dispersive X-ray spectroscopy (SEM-EDX), and transmission electron microscope-EDX. This review specifically addresses ToF-SIMS and describes some typical examples of the application of Auger and SEM-EDX.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

In this overview of diagnosis of scan logic and diagnosis driven failure analysis, the authors explore the world of diagnosis of digital semiconductors devices. After shortly outlining the technology behind diagnosis, the main part of this article describes key improvements to the basic diagnosis tools, discussing their merits for the failure analysis engineer. The article also describes the various requirements and other considerations that typically need to be taken into account to set up a full working scan diagnosis system. It summarizes the principles of design with embedded compression technologies. Finally, several successful industrial applications of diagnosis are presented.

X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.

Electronics spans a number of devices, their configurations, and properties. A challenge is to identify those electronic subjects essential for failure analysis. This article reviews the normal operation and terminal characteristics of MOSFET. It describes the electronic behavior of bridges, opens, and parametric delay defects, which is essential for understanding the symptoms of a failing IC. These electronic principles are then applied to a CMOS failure analysis technique using a power supply signature analysis.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.

This article addresses the ancillary issues regarding the nanoprobing and characterization of transistors, probing copper metallization layers, and the various imaging techniques. The discussion includes several characterization examples of known transistor failure types, namely four probe transistor characterization, two probe transistor characterization, and probing and characterizing metallization issues. The imaging techniques discussed are those that are specific to atomic force nanoprober or scanning electron microscope based tools. They are current contrast imaging, scanning capacitance imaging, e-beam absorbed current imaging, e-beam induced current imaging, e-beam induced resistance change imaging, and active voltage contrast imaging.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.