This article reviews the basic physics behind active photon injection for local photocurrent generation in silicon and thermal laser stimulation along with standard scanning optical microscopy failure analysis tools. The discussion includes several models for understanding the local thermal effects on metallic lines, junctions, and complete devices. The article also provides a description and case study examples of multiple photocurrent and thermal injection techniques. The photocurrent examples are based on Optical Beam-Induced Current and Light-Induced Voltage Alteration. The thermal stimulus examples are Optical Beam-Induced Resistance Change/Thermally-Induced Voltage Alteration and Seebeck Effect Imaging. Lastly, the article discusses the application of solid immersion lenses to improve spatial resolution.

Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

This article provides an introduction to the dynamic random access memory (DRAM) operation with a focus to localization techniques of the defects combined with some physical failure analysis examples and case studies for memory array failures. It discusses the electrical measurement techniques for array failure analysis. The article then presents know-how-based analysis techniques of array failures by bitmap classification. The limits of bitmapping that lead to well-known localization techniques like thermally induced voltage alteration and optical beam induced resistance change are also discussed. The article concludes by providing information on soft defect localization techniques.

In the Semiconductor I/C industry, it has been well documented that the proportion of factory and customer field returns attributed to device damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40 to 50%. This study entailed EOS and ESD simulation using a variety of models, namely the Human Body Model (HBM), the Charged Device Model (CDM) and the so-called Machine Model (MM), and then conducting electrical and physical failure analysis and comparing the results with documented analyses performed on customer field returns and factory failures. It is shown that a distinction can be made between EOS and ESD failures and between the characteristic failure signatures produced by the ESD models. The CDM physical failure location is at the input buffer and in the gate oxide, where as both HBM and MM failures occur mostly in the contacts at the input protection structures.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.

This chapter assesses the capabilities and limitations of electric fault isolation (EFI) technology, the measurement challenges associated with new device architectures, and the pathways for improvement in emission microscopy, laser stimulation, and optical probing. It also assesses the factors that influence signal strength, spatial and timing resolution, and alignment accuracy between signal response images and the physical layout of the IC.

Magnetic field imaging (MFI), generally understood as mapping the magnetic field of a region or object of interest using magnetic sensors, has been used for fault isolation (FI) in microelectronic circuit failure analysis for almost two decades. Developments in 3D magnetic field analysis have proven the validity of using MFI for 3D FI and 3D current mapping. This article briefly discusses the fundamentals of the technique, paying special attention to critical capabilities like sensitivity and resolution, limitations of the standard technique, sensor requirements and, in particular, the solution to the 3D problem, along with examples of its application to real failures in devices.

This chapter explains how to take the known facts of a specific failure, place them in a systematic context to arrive at a logical conclusion, and point to a corrective measure. It presents example examinations to describe a systematic approach to failure examination.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.

Diagnosing the root cause of a failure is particularly challenging if the symptom of the failure is not consistently observable. This article focuses on Laser Assisted Device Alteration/Soft Defect Localization (LADA/SDL), a global fault isolation technique, for detecting such failures. The discussion begins with a section describing the three steps in LADA/SDL analysis setup: create the test loop with the fail flag and loop trigger, select the laser dwell time, and select the shmoo bias point. An overview of LADA/SDL workflow is then presented followed by a brief section on time-resolved LADA. The closing pages of the article consider in detail SDL laser interaction physics and LADA laser interaction physics.

This chapter presents an overview of microprocessor and application specific integrated circuit (IC) testing. It begins with a description of key industry trends that will impact how ICs will be tested in the future. Next, it provides a brief description of the most common tests applied in the IC industry, where technical issues that are causing methodology changes are emphasized. These include functional testing, structural testing, scan-based delay testing, built-in self-testing, memory testing, analog circuit testing, system-on-a-chip testing, and reliability testing. Trends discussed have driven the development of novel focus areas in test and the chapter discusses several of those areas, including test data volume containment, test power containment, and novel methods of defect-based test.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

In this overview of diagnosis of scan logic and diagnosis driven failure analysis, the authors explore the world of diagnosis of digital semiconductors devices. After shortly outlining the technology behind diagnosis, the main part of this article describes key improvements to the basic diagnosis tools, discussing their merits for the failure analysis engineer. The article also describes the various requirements and other considerations that typically need to be taken into account to set up a full working scan diagnosis system. It summarizes the principles of design with embedded compression technologies. Finally, several successful industrial applications of diagnosis are presented.

Failure investigation is an integral part of any design and manufacturing operation, providing critical information to solve manufacturing problems and assist in redesigns. This chapter addresses several aspects of failure investigation, beginning with the challenges of organizing such efforts and the need to define a clear and concise goal, direction, and plan prior to the investigation. It covers the causes of failure and the training and education organizations require to understand and prevent them. The chapter emphasizes the importance of discovering the root cause of failures, and uses examples to explain the factors involved and how to recognize them when the first appear.

A cardon shaft operating in an aircraft engine failed and was taken out and analyzed to determine the cause. A photograph of the broken shaft in the as-received condition shows the location and orientation of the fracture. The fracture surface appeared smooth, indicating that a considerable amount of rubbing occurred after the shaft broke. SEM fractography revealed deformation marks and elongated dimples, typical of shear overloads, along with other details. Based on their analysis, investigators concluded that the cardan shaft failed under torsional overload. They also cited a need for a more detailed examination of the driven end of the shaft.