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Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110016
EISBN: 978-1-62708-247-1
... Abstract Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis...
Abstract
Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110550
EISBN: 978-1-62708-247-1
... Abstract The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support...
Abstract
The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.
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in X-Ray Imaging Tools for Electronic Device Failure Analysis[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 5 Examples of packaging failure analysis with 2D projection type x-ray imaging system. Images provided by Phoenix |x-ray, a division of GE Sensing and Inspection Technology.
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in X-Ray Imaging Tools for Electronic Device Failure Analysis[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 7 (a) Volume rendering of a flip chip packaging with voxel size of 7 um. (b) Volume rendering of two neighboring BGA solder joints with cross sectional images to show solder contact with pad.
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in Non-destructive Techniques for Advanced Board Level Failure Analysis
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 1 Trend overview for semiconductor packaging integration on board and system level. [2]
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Published: 01 August 2013
Fig. 6.7 Relative uses of aluminum. Packaging includes beverage cans. Trans-portation includes cars, trucks, and aircraft.
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Published: 01 April 2004
Fig. 4.38 Predicted time for moisture to permeate various packaging materials in one geometry. Adapted from Traeger [1976 ]
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Published: 01 August 1999
Fig. 13 Penetration of the aluminum foil vapor barrier on laminated packaging. The interior of the package is back illuminated, showing the loss of aluminum foil to filiform attack. Light microscopy. 10×
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Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110067
EISBN: 978-1-62708-247-1
... Abstract The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents...
Abstract
The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.
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in Silicon Device Backside De-Processing and Fault Isolation Techniques
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 1 A packaged unit mounted on a stainless steel parallel polishing fixture is shown. The yellow triangle indicate the first pin location.
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in 2.5D and 3D Packaging Failure Analysis Techniques
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 9 Cross-sectional view of a 2.5D packaged module. The image attached here is just prior to reaching the solder bump and micropillar center for further fault isolation.
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in 2.5D and 3D Packaging Failure Analysis Techniques
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 22 Lid removal process. (a) Diagram of package (b) top surface of lid to be removed (c) Perimeter of lid removed with CNC high speed milling machine (d) Package after remainder of lid removed and TIM cleaned off
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in Failure Analysis Techniques and Methods for Microelectromechanical Systems (MEMS)[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 1 Examples of different MEMS microphone package implementations. The left column are the tops of the parts, and the right column are the corresponding bottoms. In the right column, the hole that admits the sound to the MEMS is apparent on each part.
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in Failure Analysis Techniques and Methods for Microelectromechanical Systems (MEMS)[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 26 Method for measuring hermeticity for 0-level packages for RF-MEMS. From [61] .
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in Failure Analysis Techniques and Methods for Microelectromechanical Systems (MEMS)[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 27 SAM image of one corner of a 0-level package: a Si cap bonded to Si substrate with PbSn solder as sealing ring. The picture shows incomplete sealing by the solder [66] .
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in X-Ray Imaging Tools for Electronic Device Failure Analysis[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 3 Virtual cross section examples of package-level defects that are commonly imaged with 3D X-ray Microscopy tools [13] .
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in X-Ray Imaging Tools for Electronic Device Failure Analysis[1]
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 8 Optical image of a mechanical cross section through the package. The different sizes of TSV, Cu-pillar micro bumps (top to bottom die) and C4 bumps (bottom die to substrate) are clearly visible.
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in Acoustic Microscopy of Semiconductor Packages
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 1 Coefficient of thermal expansion mismatches in plastic IC packages.
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in Acoustic Microscopy of Semiconductor Packages
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 2 The inspection of IC packages with pulse-echo acoustic microscopy.
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in Acoustic Microscopy of Semiconductor Packages
> Microelectronics Failure Analysis: Desk Reference
Published: 01 November 2019
Figure 10 Time-of-flight image of a cavity-down BGA package. Darker areas are deeper in the package. A 3-D view is shown to assist visualization.
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