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masking

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Image
Published: 01 December 2003
Fig. 2 Masking of blind tapped holes on a component for plasma nitriding. More
Image
Published: 30 November 2023
Fig. 4.27 (a) Working principle of the automatic core setter. (b) Core mask with vacuum ports. Source: Ref 7 More
Image
Published: 01 December 2003
Fig. 11 Add acid to water, not vice versa. Wear a full apron, a full face mask, rubber gloves, long sleeves, and shoe protection. More
Series: ASM Technical Books
Publisher: ASM International
Published: 23 January 2020
DOI: 10.31399/asm.tb.stemsem.t56000001
EISBN: 978-1-62708-292-1
... information on imaging modes, detector positioning and alignment, and the effect of contrast reversal. It also discusses beam convergence and angular selectivity, the use of application-specific masks, and how to generate grain orientation maps for different material systems. diffraction imaging...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 December 2003
DOI: 10.31399/asm.tb.pnfn.t65900089
EISBN: 978-1-62708-350-8
.... Other important considerations discussed include the hollow cathode effect, sputter cleaning, furnace loading, pressure/voltage relationships, workpiece masking, and furnace configuration options. The chapter describes five methods of cooling parts from the process temperature to an acceptable exposure...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 December 2003
DOI: 10.31399/asm.tb.pnfn.t65900163
EISBN: 978-1-62708-350-8
... widely used, because it is least expensive in relation to other types of plated deposition. However, it is still an expensive method—not so much because of the copper plate cost, but because of the labor-intensive part preparation required. All of the areas to be nitrided must be masked prior to copper...
Series: ASM Technical Books
Publisher: ASM International
Published: 23 January 2020
DOI: 10.31399/asm.tb.stemsem.9781627082921
EISBN: 978-1-62708-292-1
Image
Published: 01 November 2019
Figure 22 STEM-BF image of a via in a test structure. The contrast at the interface is masked by diffraction effects. More
Image
Published: 01 March 2002
Fig. 7.32 Procedure to mount steel wire specimens. (a) Wires are placed in drilled holes in the mount. (b) A masking tape dam is provided to hold the castable epoxy around the specimens. 1.2× More
Image
Published: 01 September 2008
Fig. 18 Region adjacent to the fractured region showing a transgranular crack generated in the casting process and masked by material deformation during the radio machining process, with propagation directed to the internal diameter More
Image
Published: 01 June 2016
Fig. 7.18 Typical pyramidal fin prepared by cold spraying. Image at left illustrates the masking technique. Microstructures show (a) top view and (b) cross section of typical fin deposition. Source: Ref 7.5 More
Image
Published: 01 June 2016
Fig. 10.9 Photos showing coating development for hemispherical head. (a) Coated dishes (with matching geometry to the apex) used in the optimization of a curved spray pattern. (b) Apex coated using an XY pattern with masking. (c) Coated hemisphere sectioned for characterization. (d) Computer More
Image
Published: 01 April 2004
the piezoelectric elements and the substrate, the soldered joints must be of a specified thickness. This was achieved using tungsten spacer wires in each joint and a spring-loaded jig to apply a compressive stress to each element during the process cycle. Also shown is the mask used to apply the metallization More
Series: ASM Technical Books
Publisher: ASM International
Published: 01 December 2000
DOI: 10.31399/asm.tb.htgpge.t67320159
EISBN: 978-1-62708-347-8
... layer by chemical means is not advisable. Allowable white layer should not exceed 0.0127 mm (0.0005 in.) and shall be of single phase Fe 4 N composition. For selective ion nitriding, masking by mechanical means such as plate covers, which act as barriers between the glow of discharge and the part...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 March 2001
DOI: 10.31399/asm.tb.secwr.t68350195
EISBN: 978-1-62708-315-7
Series: ASM Technical Books
Publisher: ASM International
Published: 30 November 2023
DOI: 10.31399/asm.tb.ceeg.t59370059
EISBN: 978-1-62708-447-5
... or masks before the drag is compacted. The fixture or the mask is positioned over the mold, either manually or by using a manipulator, and the cores are released. The mold-closing pins or other pins provided in the core print enable accurate positioning. High-production machines use a dedicated device...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110144
EISBN: 978-1-62708-247-1
... be carefully avoided in a vacuum chamber. Ultraviolet light is created with fluorine which may begin to erase NVM memory. Very slow removal process. Package masking may be required to prevent etch outside of target zone. Silver can react and contaminate the surface with fluorine based plasma...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110279
EISBN: 978-1-62708-247-1
... are modeled to ensure speed, timing and other performance metrics are met. Circuit layout is then sent to the mask shop to manufacture lithography masks using a process called tape out. Semiconductor Manufacturing The manufacturing process of a semiconductor product is one of the most complex...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110262
EISBN: 978-1-62708-247-1
... MPT layers (e.g., Litho-Etch-Litho-Etch). In leading-edge technologies (e.g., 7nm), there can be several mask layers involved to create a single IC layer. CADNav tools have accommodated for these advancements by ensuring that the database matches the physical IC, regardless of the number of mask...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110351
EISBN: 978-1-62708-247-1
... step in bring a semiconductor product to market. Because the tooling (aka the masks) for an IC can be so expensive and time consuming, re-spins of the mask set must be minimized. So, circuit edits to emulate a mask change are a primary way to reduce development costs. Figure 1 A Pt strap...