Search Results for lapping

The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.