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insulated-gate bipolar transistors

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Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110180
EISBN: 978-1-62708-247-1
.... If the internal voltage drop between Source and Body exceeds ca. 0.5V, Source serves as Emitter and Drain as Collector, and the body works like a Base. It is a transistor parallel to the FET but can’t be turned off by the gate. PE can identify the parasitic bipolar operation. If the I/O device is large enough...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110652
EISBN: 978-1-62708-247-1
... transistors (Weff=45micron). One transistor in Fig. 25 is connected to VSS and the other to VCC with the gates connected to the substrate ground via a high by a value resistor in order to initiate bipolar action by dynamic gate to substrate voltage. A standard curve tracer (Tektronix 575) and a manual...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 August 2015
DOI: 10.31399/asm.tb.piht2.t55050025
EISBN: 978-1-62708-311-9
... that is sometimes measured and monitored is the workpiece temperature throughout the heating cycle. In addition some insulated-gate bipolar transistor power supplies float the frequency to make tuning easier. It may be important for production part approval process validation that the output be fixed, once tuned...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110244
EISBN: 978-1-62708-247-1
... discriminate between the buffer’s 4 transistors. The colors represent the polarity of the signal, with red indicating that the gate has a positive net amplitude and green indicating it has a negative net amplitude (with respect to the baseline). Figure 12 (a) LVP waveform of a single pulse navigating...
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110111
EISBN: 978-1-62708-247-1
... complex and the industry keeps advancing packaging technologies like flip-chip, stacked die, Wafer-Level- packaging, System-in-Package, TSV, 2.5D, FanOut, etc., present Fault Isolation (FI) tools and techniques are having increasing difficulty in meeting Failure Analysis (FA) needs [1] . With gate sizes...