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Book Chapter
Die-Level Roadmap: Post-Isolation Domain
Available to PurchaseSeries: ASM Technical Books
Publisher: ASM International
Published: 01 November 2023
DOI: 10.31399/asm.tb.edfatr.t56090109
EISBN: 978-1-62708-462-8
... 2010, 2011, and international co-Chair in 2013. Phil Kaszuba, Consultant, USA, <underline><email href="mailto:[email protected]">[email protected]</email></underline> Phil Kaszuba, FASM, is a retired senior member of the technical staff for GlobalFoundries. He holds a B.S.E.E. from...
Abstract
The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2023
DOI: 10.31399/asm.tb.edfatr.9781627084628
EISBN: 978-1-62708-462-8