Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

In the Semiconductor I/C industry, it has been well documented that the proportion of factory and customer field returns attributed to device damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40 to 50%. This study entailed EOS and ESD simulation using a variety of models, namely the Human Body Model (HBM), the Charged Device Model (CDM) and the so-called Machine Model (MM), and then conducting electrical and physical failure analysis and comparing the results with documented analyses performed on customer field returns and factory failures. It is shown that a distinction can be made between EOS and ESD failures and between the characteristic failure signatures produced by the ESD models. The CDM physical failure location is at the input buffer and in the gate oxide, where as both HBM and MM failures occur mostly in the contacts at the input protection structures.

Root cause of failure in automotive electronics cannot be explained by the failure signatures of failed devices. Deeper investigations in these cases reveals that a superimposition of impact factors, which can never be represented by usual qualification testing, caused the failure. This article highlights some of the most frequent early life failure types in automotive applications. It describes some of the critical things to be considered while handling packages and printed circuit board layout. The article also provides information on failure anamnesis that shows how to use history, failure signatures, environmental conditions, regional failure occurrences, user profile issues, and more in the failure analysis process to improve root cause findings.

Electronics spans a number of devices, their configurations, and properties. A challenge is to identify those electronic subjects essential for failure analysis. This article reviews the normal operation and terminal characteristics of MOSFET. It describes the electronic behavior of bridges, opens, and parametric delay defects, which is essential for understanding the symptoms of a failing IC. These electronic principles are then applied to a CMOS failure analysis technique using a power supply signature analysis.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

This chapter provides an overview of the tools and techniques used to examine failure specimens and the wealth of information that can be obtained from fracture surfaces, cracks, wear patterns, and other such features. It discusses the use of metallography, fractography, and optical and electron microscopy. It presents a number of images recorded using these methods and explains what they reveal about the mode of fracture and the state of the component prior to failure.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

Time-domain based characterization methods, mainly time-domain reflectometry (TDR) and time-domain transmissometry (TDT), have been used to locate faults in twisted cables, telegraph lines, and connectors in the electrical and telecommunication industry. This article provides a brief review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly made it a well-adopted tool in the industry. The third part of this article introduces a new method which combines impulse signal and the TDT concept, and discusses a combo TDR and TDT method. Cases studies and application notes are shared and discussed for each technique. Application benefits and limitations of these techniques (TDR, EOTPR, and combo TDR/TDT) are summarized and compared.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

This chapter describes the characteristic damage of a mid-air explosion and how it appears in metal debris recovered from crash sites of downed aircraft. It explains that explosive forces produce telltale signs such as petaling, curling, spalling, spikes, reverse slant fractures, and metal deposits. Explosive forces can also cause ductile metals such as aluminum to disintegrate into tiny pieces and are associated with chemicals that leave residues along with numerous craters on metal surfaces. The chapter provides examples of the different types of damage as revealed in the investigation of two in-flight bombings.

This article addresses the ancillary issues regarding the nanoprobing and characterization of transistors, probing copper metallization layers, and the various imaging techniques. The discussion includes several characterization examples of known transistor failure types, namely four probe transistor characterization, two probe transistor characterization, and probing and characterizing metallization issues. The imaging techniques discussed are those that are specific to atomic force nanoprober or scanning electron microscope based tools. They are current contrast imaging, scanning capacitance imaging, e-beam absorbed current imaging, e-beam induced current imaging, e-beam induced resistance change imaging, and active voltage contrast imaging.

This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

This chapter details the vibration limits for gearboxes. It focuses on critical speed and peak load. The chapter presents vibration measurement and analysis, which provides a quick and relatively inexpensive way to detect and identify mechanical problems before they become more serious and costly.

Diagnosing the root cause of a failure is particularly challenging if the symptom of the failure is not consistently observable. This article focuses on Laser Assisted Device Alteration/Soft Defect Localization (LADA/SDL), a global fault isolation technique, for detecting such failures. The discussion begins with a section describing the three steps in LADA/SDL analysis setup: create the test loop with the fail flag and loop trigger, select the laser dwell time, and select the shmoo bias point. An overview of LADA/SDL workflow is then presented followed by a brief section on time-resolved LADA. The closing pages of the article consider in detail SDL laser interaction physics and LADA laser interaction physics.

Post-mortem analysis of photovoltaic modules that have degraded performance is essential for improving the long term durability of solar energy. This article focuses on a general procedure for analyzing a failed module. The procedure includes electrical characterization followed by thermal imaging such as forward bias, reverse bias, and lock-in, and emission imaging such as electroluminescence and photoluminescence imaging.

In this overview of diagnosis of scan logic and diagnosis driven failure analysis, the authors explore the world of diagnosis of digital semiconductors devices. After shortly outlining the technology behind diagnosis, the main part of this article describes key improvements to the basic diagnosis tools, discussing their merits for the failure analysis engineer. The article also describes the various requirements and other considerations that typically need to be taken into account to set up a full working scan diagnosis system. It summarizes the principles of design with embedded compression technologies. Finally, several successful industrial applications of diagnosis are presented.

This chapter focuses on common failure characteristics exhibited by mechanical and electrical components. The topic is considered from two perspectives: one possibility is that the system failed because parts were nonconforming to drawing requirements and another possibility is that the system failed even though all parts in the system met their drawing requirements. The common failures discussed in this chapter include those associated with metallic components, composite materials, plastic components, ceramic components, and electrical and electronic components.

Magnetic field imaging (MFI), generally understood as mapping the magnetic field of a region or object of interest using magnetic sensors, has been used for fault isolation (FI) in microelectronic circuit failure analysis for almost two decades. Developments in 3D magnetic field analysis have proven the validity of using MFI for 3D FI and 3D current mapping. This article briefly discusses the fundamentals of the technique, paying special attention to critical capabilities like sensitivity and resolution, limitations of the standard technique, sensor requirements and, in particular, the solution to the 3D problem, along with examples of its application to real failures in devices.

Laser Voltage Probing (LVP) is a key enabling technology that has matured into a well-established and essential analytical optical technique that is crucial for observing and evaluating internal circuit activity. This article begins by providing an overview on LVP history and LVP theory, providing information on electro-optical effects and free-carrier effects. It then focuses on commercially available continuous wave LVP systems. Alternative optoelectronic imaging and probing technologies for fault isolation, namely frequency mapping and laser voltage tracing, are also discussed. The subsequent section provides information on the use of Visible Laser Probing. The article closes with some common LVP observations/considerations and limitations and future work concerning LVP.