X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.

This chapter focuses on the failure aspects of tool steels. The discussion covers the classification, chemical composition, main characteristics, and several failures of tool steels and their relation to heat treatment. The tool steels covered are hot work, cold work, plastic mold, and high-speed tool steels.

In this overview of diagnosis of scan logic and diagnosis driven failure analysis, the authors explore the world of diagnosis of digital semiconductors devices. After shortly outlining the technology behind diagnosis, the main part of this article describes key improvements to the basic diagnosis tools, discussing their merits for the failure analysis engineer. The article also describes the various requirements and other considerations that typically need to be taken into account to set up a full working scan diagnosis system. It summarizes the principles of design with embedded compression technologies. Finally, several successful industrial applications of diagnosis are presented.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

Root cause of failure in automotive electronics cannot be explained by the failure signatures of failed devices. Deeper investigations in these cases reveals that a superimposition of impact factors, which can never be represented by usual qualification testing, caused the failure. This article highlights some of the most frequent early life failure types in automotive applications. It describes some of the critical things to be considered while handling packages and printed circuit board layout. The article also provides information on failure anamnesis that shows how to use history, failure signatures, environmental conditions, regional failure occurrences, user profile issues, and more in the failure analysis process to improve root cause findings.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

This chapter focuses on what can cause a system to fail and addresses the challenge in approaching a system failure. It then examines the steps involved in the four-step problem-solving process: defining the problem, identifying all potential failure causes and evaluating the likelihood of each, identifying the potential solutions, and identifying the best solution. The chapter concludes by describing the responsibilities of a failure analysis team.

This chapter provides a comprehensive overview over all phenomena related to Voltage Contrast (VC) mechanisms in SEM and FIB. The multiple advantages, possibilities, and limits of active and passive VC failure localization are systemized and discussed. The knowledge of all facts influencing the VC generation (capacitance, leakage, doping, and circuitry) is very helpful for successful failure localization.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

This chapter briefly outlines some of the basic aspects of failure analysis, describing some of the basic steps and major concerns in conducting a failure analysis. A brief review of failure types from fracture, distortion, wear-assisted failure, and environmentally assisted failure (corrosion) is also provided.

This article presents six case studies of failures with steel forgings. The case studies covered are crankshaft underfill; tube bending; spade bit; trim tear; upset forging; and avoidance of flow through, lap, and crack. The case studies illustrate difficulties encountered in either cold forging or hot forging in terms of preforge factors and/or discontinuities generated by the forging process. Supporting topics that are discussed in the case studies include validity checks for buster and blocker design, lubrication and wear, mechanical surface phenomenon, forging process design, and forging tolerances. Wear, plastic deformation processes, and laws of friction are introduced as a group of subjects that have been considered in the case studies.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

This chapter provides an overview of the possible mechanisms of failure for heat treated steel components and discusses the techniques for examining fractures, ductile and brittle failures, intergranular failure mechanisms, and fatigue. It begins with a description of the general sources of component failure. This is followed by a section on the stages of a failure analysis, which can proceed one after the other or occur at the same time. These stages of analysis are collection of background data, preliminary visual examination, nondestructive testing, selection and preservation of specimens, mechanical testing, macroexamination, microexamination, metallographic examination, determination of the fracture mechanism, chemical analysis, exemplar testing, and analysis and writing the report. The chapter ends with a discussion on various processes involved in the determination of the fracture mechanism.

Failure analysis of steel welds may be divided into three categories. They include failures due to design deficiencies, weld-related defects usually found during inspection, and failures in field service. This chapter emphasizes the failures due to various discontinuities in the steel weldment. These include poor workmanship, a variety of hydrogen-assisted cracking failures, stress-corrosion cracking, fatigue, and solidification cracking in steel welds. Hydrogen-assisted cracking can appear in four common forms, namely underbead or delayed cracking, weld metal fisheyes, ferrite vein cracking, and hydrogen-assisted reduced ductility.

Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.