This appendix focuses on procedures, techniques, and precautions associated with the investigation and analysis of metallurgical failures that occur in service. It describes the steps of an orderly failure analysis from collecting and examining samples to performing mechanical and nondestructive tests, preparing and examining fractographs and micrographs, determining failure mode, writing the report, and developing follow-up recommendations. It also examines the fundamental mechanisms of failure, why they occur, and how to identify them by their characteristic features.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

Post-mortem analysis of photovoltaic modules that have degraded performance is essential for improving the long term durability of solar energy. This article focuses on a general procedure for analyzing a failed module. The procedure includes electrical characterization followed by thermal imaging such as forward bias, reverse bias, and lock-in, and emission imaging such as electroluminescence and photoluminescence imaging.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

Passive components can be broadly divided into capacitors, resistors, and inductors. Failure analysis of these components helps determine the root cause and improve the overall quality and reliability of the electronic systems. This article describes different failure analysis approaches used for these components. It discusses different types of capacitors along with their constructions and failure modes. The types include tantalum, aluminum electrolytic, multi-layered ceramics, film, and super capacitors. The article then provides a discussion on the two common types of inductors, namely, common mode choke coil and surface mount powder choke coil.

Electronics spans a number of devices, their configurations, and properties. A challenge is to identify those electronic subjects essential for failure analysis. This article reviews the normal operation and terminal characteristics of MOSFET. It describes the electronic behavior of bridges, opens, and parametric delay defects, which is essential for understanding the symptoms of a failing IC. These electronic principles are then applied to a CMOS failure analysis technique using a power supply signature analysis.

This article is a compilation of terms and definitions related to failure analysis that have been addressed in the proceedings of the International Symposium for Testing and Failure Analysis.

This chapter discusses the importance of failure analysis and the role it plays in a society driven by technological advancement. It explains why failure rates are highest in the early and later stages of the life of any product and shows the extent to which failure rates increase when products are subjected to an aggressive operating environment.

This chapter discusses the basic steps of a failure investigation. It explains that the first step is to gather and document information about the failed component and its operating history. It advises investigators to visit the failure site as soon as possible to record damages and collect test specimens for subsequent examination and chemical analysis. It also discusses the role of mechanical property testing, the use of nondestructive evaluation, and the final step of generating a report.

This chapter discusses some of the more advanced methods and procedures used in failure analysis, including in-service material sampling, in situ microstructure analysis, and a form of punch testing that can determine the fracture toughness of any material from a tiny specimen. The chapter also covers quantitative fractography, fracture surface topography analysis, and the use of oxide dating as well as fault tree and failure modes and effects analysis (FMEA) and computational techniques.

This chapter discusses the role of failure analysis in cases involving product liability, property damage, and personal injury litigation. It also explains how material science and technology shed light on criminal activities such as smuggling, counterfeiting, theft, and the willful destruction of property.

This chapter discusses some of the ways that the lessons learned from failures have benefitted society, leading to improved product designs, better materials, safer industrial processes, and more robust codes and standards. It also provides several examples of how the technology and procedures associated with aviation security have been upgraded in the wake of air disasters.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

The management of a failure analysis (FA) laboratory requires a broad range of activities to optimize the efficiency of the operation. The purpose of this article is to stimulate readers to consider the various aspects of FA laboratory operations and their respective business management requirements. The various aspects include: staffing, laboratory organization, lab design and operations, strategic development, financial management, and metrics and measurements. References for further reading and examples of resource materials are also included.

X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.