Time-domain based characterization methods, mainly time-domain reflectometry (TDR) and time-domain transmissometry (TDT), have been used to locate faults in twisted cables, telegraph lines, and connectors in the electrical and telecommunication industry. This article provides a brief review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly made it a well-adopted tool in the industry. The third part of this article introduces a new method which combines impulse signal and the TDT concept, and discusses a combo TDR and TDT method. Cases studies and application notes are shared and discussed for each technique. Application benefits and limitations of these techniques (TDR, EOTPR, and combo TDR/TDT) are summarized and compared.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

Magnetic field imaging (MFI), generally understood as mapping the magnetic field of a region or object of interest using magnetic sensors, has been used for fault isolation (FI) in microelectronic circuit failure analysis for almost two decades. Developments in 3D magnetic field analysis have proven the validity of using MFI for 3D FI and 3D current mapping. This article briefly discusses the fundamentals of the technique, paying special attention to critical capabilities like sensitivity and resolution, limitations of the standard technique, sensor requirements and, in particular, the solution to the 3D problem, along with examples of its application to real failures in devices.