This article discusses electrical testing and recommended procedures for determining the electrical properties of insulating materials, with particular emphasis on plastics. It describes the electrical characteristics of various forms of plastics and also presents definitions of the terms used in connection with testing and specifying plastics for electrical applications.

This article provides an introduction to the dynamic random access memory (DRAM) operation with a focus to localization techniques of the defects combined with some physical failure analysis examples and case studies for memory array failures. It discusses the electrical measurement techniques for array failure analysis. The article then presents know-how-based analysis techniques of array failures by bitmap classification. The limits of bitmapping that lead to well-known localization techniques like thermally induced voltage alteration and optical beam induced resistance change are also discussed. The article concludes by providing information on soft defect localization techniques.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

Education and training play an important role if the failure analyst is to be successful in his or her work. This article discusses the history of training activities in the failure/product analysis discipline and describes where this area is heading. It provides information on three areas of education and training that should be given to the analyst for him or her to be successful developing and fielding modern semiconductor components: analysis process, technology, and technique training.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.

Most of the counterfeit parts detected in the electronics industry are either novel or surplus parts or salvaged scrap parts. This article begins by discussing the type of parts used to create counterfeits. It discusses the three most commonly used methods used by counterfeiters to create counterfeits. These include relabeling, refurbishing, and repackaging. The article presents a systematic inspection methodology that can be applied for detecting signs of possible part modifications. The methodology consists of external visual inspection, marking permanency tests, and X-ray inspection followed by material evaluation and characterization. These processes are typically followed by evaluation of the packages to identify defects, degradations, and failure mechanisms that are caused by the processes (e.g., cleaning, solder dipping of leads, reballing) used in creating counterfeit parts.

One of the rotor bearings in an electric motor failed, producing excessive vibrate. The bearing was removed and disassembled, revealing craters and bruises on the inner ring raceway and balls along with evidence of melting and burning of metal. Scanning electron microscopy revealed metal particles near the craters, and energy-dispersive x-ray analysis showed that slivers recovered from the grease had the same composition as the bearing raceway and balls. Based on these observations, it was concluded that the bearing failed due to electrostatic discharge, which would have led to seizure if it continued. The report recommends the use of electrically conductive grease and proper grounding practices.

This appendix is a compilation of suggested analysis methods for suspected component failure causes.

This chapter discusses the various failure analysis techniques for microelectromechanical systems (MEMS), focusing on conventional semiconductor manufacturing processes and materials. The discussion begins with a section describing the advances in integration and packaging technologies that have helped drive the further proliferation of MEMS devices in the marketplace. It then shows some examples of the top MEMS applications and quickly discusses the fundamentals of their workings. The next section describes common failure mechanisms along with techniques and challenges in identifying them. The chapter also provides information on the testing of MEMS devices. It covers the two common challenges in sample preparation for MEMS: decapping, or opening up the package, without disturbing the MEMS elements; and removing MEMS elements for analysis. Finally, the chapter discusses the aspects of failure analysis techniques that are of particular interest to MEMS.

This article presents a general overview of outdoor weather aging factors, their effects on plastic materials, and the accelerated test methods that can be used to estimate the reaction of a plastic component during actual use. Weather and radiation factors that contribute to degradation in plastics include temperature variations, moisture, sunlight, oxidation, microbiologic attack, and other environmental elements. The article also describes the tests used to predict the behavior of a plastic material to outdoor exposure, discussing the use of xenon arc lamp for the weatherometer and fadeometer and the use of fluorescent sunlamp in test devices.

Time-domain based characterization methods, mainly time-domain reflectometry (TDR) and time-domain transmissometry (TDT), have been used to locate faults in twisted cables, telegraph lines, and connectors in the electrical and telecommunication industry. This article provides a brief review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly made it a well-adopted tool in the industry. The third part of this article introduces a new method which combines impulse signal and the TDT concept, and discusses a combo TDR and TDT method. Cases studies and application notes are shared and discussed for each technique. Application benefits and limitations of these techniques (TDR, EOTPR, and combo TDR/TDT) are summarized and compared.

Magnetic field imaging (MFI), generally understood as mapping the magnetic field of a region or object of interest using magnetic sensors, has been used for fault isolation (FI) in microelectronic circuit failure analysis for almost two decades. Developments in 3D magnetic field analysis have proven the validity of using MFI for 3D FI and 3D current mapping. This article briefly discusses the fundamentals of the technique, paying special attention to critical capabilities like sensitivity and resolution, limitations of the standard technique, sensor requirements and, in particular, the solution to the 3D problem, along with examples of its application to real failures in devices.

This article is a compilation of terms and definitions related to failure analysis that have been addressed in the proceedings of the International Symposium for Testing and Failure Analysis.

This appendix is a glossary of terms related to induction heat treating.

In 1924, the American Society for Testing and Materials (ASTM) organized the symposium "Corrosion and Heat Resisting Alloys, and Electrical Resistance Alloys." It was the beginning of a major role that ASTM played in the history of stainless steel. This chapter provides information on the papers presented at the 1924 symposium. It also describes the role of ASTM in stainless steel standardization after the 1924 symposium.

This appendix is a compilation of terms and definitions related to corrosion.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.