Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

This chapter discusses composite testing procedures, including tension, compression, shear, flexure, and fracture toughness testing as well as adhesive shear, peel, and honeycomb flatwise tension testing. It also discusses specimen preparation, environmental conditioning, and data analysis.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.

A product pedigree describes its design and how it was built and shows that it was built in accordance with the drawings and other documentation defining the product configuration. Evaluating the pedigree of a failed product can help to rule in or rule out hypothesized failure causes. This chapter describes various areas that can be examined by the failure analysis team to assess the pedigree of the failed system. If the failure analysis team suspects product pedigree anomalies it should confirm conformance through independent means.

Scanning Probe Microscope (SPM) has an increasing important role in the development of nanoscale semiconductor technologies. This article presents a detailed discussion on various SPM techniques including Atomic Force Microscopy (AFM), Scanning Kelvin Probe Microscopy, Scanning Capacitance Microscopy, Scanning Spreading Resistance Microscopy, Conductive-AFM, Magnetic Force Microscopy, Scanning Surface Photo Voltage Microscopy, and Scanning Microwave Impedance Microscopy. An overview of each SPM technique is given along with examples of how each is used in the development of novel technologies, the monitoring of manufacturing processes, and the failure analysis of nanoscale semiconductor devices.

This article provides an introduction to the dynamic random access memory (DRAM) operation with a focus to localization techniques of the defects combined with some physical failure analysis examples and case studies for memory array failures. It discusses the electrical measurement techniques for array failure analysis. The article then presents know-how-based analysis techniques of array failures by bitmap classification. The limits of bitmapping that lead to well-known localization techniques like thermally induced voltage alteration and optical beam induced resistance change are also discussed. The article concludes by providing information on soft defect localization techniques.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

In this overview of diagnosis of scan logic and diagnosis driven failure analysis, the authors explore the world of diagnosis of digital semiconductors devices. After shortly outlining the technology behind diagnosis, the main part of this article describes key improvements to the basic diagnosis tools, discussing their merits for the failure analysis engineer. The article also describes the various requirements and other considerations that typically need to be taken into account to set up a full working scan diagnosis system. It summarizes the principles of design with embedded compression technologies. Finally, several successful industrial applications of diagnosis are presented.

This article addresses the ancillary issues regarding the nanoprobing and characterization of transistors, probing copper metallization layers, and the various imaging techniques. The discussion includes several characterization examples of known transistor failure types, namely four probe transistor characterization, two probe transistor characterization, and probing and characterizing metallization issues. The imaging techniques discussed are those that are specific to atomic force nanoprober or scanning electron microscope based tools. They are current contrast imaging, scanning capacitance imaging, e-beam absorbed current imaging, e-beam induced current imaging, e-beam induced resistance change imaging, and active voltage contrast imaging.

This chapter provides an overview of the possible mechanisms of failure for heat treated steel components and discusses the techniques for examining fractures, ductile and brittle failures, intergranular failure mechanisms, and fatigue. It begins with a description of the general sources of component failure. This is followed by a section on the stages of a failure analysis, which can proceed one after the other or occur at the same time. These stages of analysis are collection of background data, preliminary visual examination, nondestructive testing, selection and preservation of specimens, mechanical testing, macroexamination, microexamination, metallographic examination, determination of the fracture mechanism, chemical analysis, exemplar testing, and analysis and writing the report. The chapter ends with a discussion on various processes involved in the determination of the fracture mechanism.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

There are several analytical methods available that can be used in-line on whole wafers as well as off-line on de-processed products that are returned from the field. These techniques are surface analytical techniques that can be used to characterize the bulk of the material. The main six methods used in semiconductor industry are: Auger spectroscopy, dynamic secondary ion mass spectroscopy, time of flight static secondary ion mass spectroscopy (ToF-SIMS), X-ray photoelectron spectroscopy, scanning electron microscope-energy dispersive X-ray spectroscopy (SEM-EDX), and transmission electron microscope-EDX. This review specifically addresses ToF-SIMS and describes some typical examples of the application of Auger and SEM-EDX.

Electronics spans a number of devices, their configurations, and properties. A challenge is to identify those electronic subjects essential for failure analysis. This article reviews the normal operation and terminal characteristics of MOSFET. It describes the electronic behavior of bridges, opens, and parametric delay defects, which is essential for understanding the symptoms of a failing IC. These electronic principles are then applied to a CMOS failure analysis technique using a power supply signature analysis.

The management of a failure analysis (FA) laboratory requires a broad range of activities to optimize the efficiency of the operation. The purpose of this article is to stimulate readers to consider the various aspects of FA laboratory operations and their respective business management requirements. The various aspects include: staffing, laboratory organization, lab design and operations, strategic development, financial management, and metrics and measurements. References for further reading and examples of resource materials are also included.

This article provides an overview of the most common micro-analytical technique in the failure analysis laboratory: energy dispersive X-ray spectroscopy (EDS). It discusses the general characteristics, advantages, and disadvantages of some of the X-ray detectors attached to the scanning electron microscope chamber including the lithium-drifted EDS detector, silicon drift detector (SDD), and wavelength dispersive X-ray detector. The article then provides information on qualitative and quantitative X-ray analysis programs followed by a discussion on EDS elemental mapping. The discussion includes a comparison of scanning transmission electron microscope-EDS elemental mapping and mapping with an SDD. A brief section is devoted to the discussion on the artifacts that occur during X-ray mapping.

This chapter briefly outlines some of the basic aspects of failure analysis, describing some of the basic steps and major concerns in conducting a failure analysis. A brief review of failure types from fracture, distortion, wear-assisted failure, and environmentally assisted failure (corrosion) is also provided.

This chapter focuses on what can cause a system to fail and addresses the challenge in approaching a system failure. It then examines the steps involved in the four-step problem-solving process: defining the problem, identifying all potential failure causes and evaluating the likelihood of each, identifying the potential solutions, and identifying the best solution. The chapter concludes by describing the responsibilities of a failure analysis team.