Fig. 12.1 Characterization of spinning. Source: Ref 12.1 More

Fig. A3.4 Characterization of multiturn coils: (a) uneven heating pattern in a round bar obtained by a coil with an even pitch, a problem that can be corrected by (b) increasing the pitch of the central turns of the coil, (c) varying the coupling, or (d) using a longer coil. L: length More

Fig. 36 Ultrasonic attenuation for porosity characterization. Source: Ref 7 More

Figure 9 Device characterization setup using source meter (SMU) More

Figure 32 Four probe characterization (Ids vs Vgs, step Vds) of the failing transistors with the dislocation in the through the Drain to Well junction shows Id leakage when the Gate Voltage (Vg) = 0V. More

Figure 33 Four probe characterization (Ids vs Vgs, step Vds) of a passing transistors with no dislocation shows no Id leakage when the Gate Voltage (Vg) = 0V. More

Figure 35 Two probe characterization results of the failing transistor Drain with the dislocation to Well shows leakage (100uA @ 1V) when the Drain to Well junction is forward biased and leakage (8uA @ 1.8V) when the Drain to Well junction is reversed biased. More

Figure 36 Two probe characterization results for a passing transistor with no dislocation in the Drain to Well junction. There is no leakage (35uA @ 1V) when the Drain to Well junction is forward biased and no leakage when the Drain to Well junction is reversed biased (Low pA @ 1.8V). More

Figure 39 Transistor characterization results for the failing 6T – Bitcell showing the Id vs Vg curves for the BL and BLB passgate, pulldown, and pullup transistors. The Vt values are as expected and the nfet and pfet Vt values are fairly well matched. Id drive currents are in the range More

Figure 40 Transistor characterization results for a neighboring passing 6T – Bitcell showing the Id vs Vg curves for the BL and BLB passgate, pulldown, and pullup transistors. The Vt values and Id drive current values are similar to the failing bitcell. More

Figure 41 Transistor characterization results for pfet pullup transistors for the failing and several passing bitcells. The Id vs Vg curves shows the Vt value is on the high side of the distribution causing the Id drive current to be on the low side of the distribution. More

Figure 42 Transistor characterization results for nfet pulldwon transistors for the failing and several passing bitcells. The Id vs Vg curves shows the Vt value is on the low side of the distribution causing the Id drive current to be on the high side of the distribution. More

Figure 53 Id/Is vs. Vg characterization results on a linear scale for the passing BL pass gate transistor and failing BLB pass gate transistor. The failing BLB transistor shows a Vt shift and suppressed drive current and that is symmetrical for both the forward (Id) and reverse (Is) bias More

Figure 54 Id/Is vs. Vg characterization results on a log scale for the passing BL pass gate transistor and failing BLB pass gate transistor. On the log scale, the sub-threshold performance of the transistors becomes clearly visible and shows that the start of the channel inversion is delayed More

Figure 68 Characterization results for the failing MIMs capacitor (Left) vs. the results for a passing capacitor (right). The failing shorted capacitor shows uA leakage compared to the passing capacitor shows fA level leakage. More

Figure 96 Gate oxide rupture site and characterization of EBAC spatial resolution vs beam energy presented in [14] showing (a) simulation of e-beam penetration with 7kV also showing a structural cross section with dimensions. (b) 8kV had optimal localization with 10kV having reasonable More

Figure 14 (a) Wafer test sort map and (b) failure characterization bin map based on bin 3 dies from (a). The fail sub-bins are colour-coded for clear visualization of failure signature. More

Fig. 9.27 Typical analog test specimens for characterization and aging. JANNAF: Joint Army, Navy, NASA, Air Force More

Fig. 8.9 Adjustment (“characterization”) of induction heating patterns for several parts by varying the coupling distance or turn spacing. From F. W. Curtis, High Frequency Induction Heating , McGraw-Hill, New York, 1950 ( Ref 1 ) More

Fig. 14.26 Ultrasonic attenuation for porosity characterization More