The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.

This article presents methods that enable one to consistently, uniformly and quickly remove substrate silicon from units without imparting damage to the structure of interest. It provides examples of electron beam probing and backside nano-probing techniques. The electron beam probing techniques are E-beam Logic State Imaging, Electron-beam Signal Image Mapping, and E-beam Device Perturbation. Backside nano-probing techniques discussed include: Electron Beam Absorbed Current, Electron Beam Induced Resistance Change, four terminal resistance measurements, resistive gate defect identification, and circuit editing. The article also presents methods to prepare electron beam probing samples where some remaining silicon is required for the transistor functions and transmission electron microscope samples from units where the substrate silicon has been partially or completely removed.

The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

This article reviews the basic physics behind active photon injection for local photocurrent generation in silicon and thermal laser stimulation along with standard scanning optical microscopy failure analysis tools. The discussion includes several models for understanding the local thermal effects on metallic lines, junctions, and complete devices. The article also provides a description and case study examples of multiple photocurrent and thermal injection techniques. The photocurrent examples are based on Optical Beam-Induced Current and Light-Induced Voltage Alteration. The thermal stimulus examples are Optical Beam-Induced Resistance Change/Thermally-Induced Voltage Alteration and Seebeck Effect Imaging. Lastly, the article discusses the application of solid immersion lenses to improve spatial resolution.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

With the commercialization of heavier and lighter ion beams, adoption of focused ion beam (FIB) use for analysis of challenging regions of interest (ROI) has grown. In this chapter, the authors focus on highlighting commercially available and complementary FIB technologies and their implementation challenges and application trends.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

Moore's Law has driven many degree circuit features below the resolving capability of optical microscopy. Yet the optical microscope remains a valuable tool in failure analysis. This article describes the physics governing resolution and useful techniques for extracting the small details. It begins with the basic microscope column and construction. The article discusses microscope adjustments, brightfield and darkfield illumination, and microscope concepts important to liquid crystal techniques. It also discusses solid immersion lenses, infrared and ultraviolet microscopy and concludes with laser microscopy techniques such as thermal induced voltage alteration and external induced voltage alteration.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

Photon emission (PE) is one of the major optical techniques for contactless isolation of functional faults in integrated circuits (ICs) in full electrical operation. This article describes the fundamental mechanisms of PE in silicon based ICs. It presents the opportunities of contactless characterization for the most important electronic device, the MOS - Field Effect Transistor, the heart of ICs and their basic digital element, the CMOS inverter. The article discusses the specification and selection of detectors for proper PE applications. The main topics are image resolution, sensitivity, and spectral range of the detectors. The article also discusses the value and application of spectral information in the PE signal. It describes state of the art IC technologies. Finally, the article discusses the applications of PE in ICs and also I/O devices, integrated bipolar transistors in BiCMOS technologies, and parasitic bipolar effects like latch up.

Laser Voltage Probing (LVP) is a key enabling technology that has matured into a well-established and essential analytical optical technique that is crucial for observing and evaluating internal circuit activity. This article begins by providing an overview on LVP history and LVP theory, providing information on electro-optical effects and free-carrier effects. It then focuses on commercially available continuous wave LVP systems. Alternative optoelectronic imaging and probing technologies for fault isolation, namely frequency mapping and laser voltage tracing, are also discussed. The subsequent section provides information on the use of Visible Laser Probing. The article closes with some common LVP observations/considerations and limitations and future work concerning LVP.

This article addresses the ancillary issues regarding the nanoprobing and characterization of transistors, probing copper metallization layers, and the various imaging techniques. The discussion includes several characterization examples of known transistor failure types, namely four probe transistor characterization, two probe transistor characterization, and probing and characterizing metallization issues. The imaging techniques discussed are those that are specific to atomic force nanoprober or scanning electron microscope based tools. They are current contrast imaging, scanning capacitance imaging, e-beam absorbed current imaging, e-beam induced current imaging, e-beam induced resistance change imaging, and active voltage contrast imaging.

Rough grinding and polishing of mounted specimens are required to prepare the composite sample for optical analysis. This chapter describes these techniques for preparing composite materials. First, it provides information on grinding and polishing equipment and describes the processes and process variables for sample preparation. Then, the chapter discusses the processes of abrasive sizing for grinding and rough polishing. Next, it provides a summary of grinding methods, rough polishing, and final polishing. Finally, information on common polishing artifacts that can result from any of the steps is provided.

Cross-sectioning refers to the process of exposing the internal layers and printed devices below the surface by cleaving through the wafer. This article discusses in detail the steps involved in common cross-sectioning methods. These include sample preparation, scribing, indenting, and cleaving. The article also provides information on options for mounting, handling, and cleaning of samples during and after the cleaving process. The general procedures, tools required, and considerations that need to be taken into account to perform these techniques are considered.

This chapter covers basic machining and assembly operations, with an emphasis on hole preparation for mechanical fasteners. It describes manual, power feed, and automated drilling techniques as well as reaming and countersinking. It discusses various types of fasteners, including rivets, pins, and bolts, along with selection factors and special considerations for composite joints. It also includes information on interference-fit and blind fasteners as well as trimming operations, general assembly considerations, and sealing and painting procedures.

Many defects generate excessive heat during operation; this is due to the power dissipation associated with the excess current flow at the defect site. There are several thermal detection techniques for failure analysis and this article focuses on infrared thermography with lock-in detection, which detects an object's temperature from its infrared emission based on blackbody radiation physics. The basic principles and the interpretation of the results are reviewed. Some typical results and a series of examples illustrating the application of this technique are also shown. Brief sections are devoted to the discussion on liquid-crystal imaging and fluorescent microthermal imaging technique for thermal detection.