The hidden factory refers to the activities associated with scrap and rework. This chapter presents a rudimentary understanding of what sorts of things the hidden factory is doing, focusing on how to get one's arms around the rejections that occur most frequently or have the highest cost. It provides information on the use of Pareto analyses from both frequency-of-occurrence and cost perspectives to target specific areas for improvement.

This chapter provides an introduction to statistical process control and the concept of total quality management. It begins with a review of quality improvement efforts in the extrusion industry and the considerations involved in developing sampling plans and interpreting control charts. It then lays out the steps that would be followed in order to implement statistical testing for billet casting, die performance, or any other process or variable that impacts extrusion quality. The chapter concludes with an overview of the fundamentals of total quality management.

Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.

Over the revolutionary era of semiconductor technology, Computer-Aided Design Navigation (CADNav) tools have played an increasingly critical role in silicon debug and failure analysis (FA) in efforts to improve manufacturing yield while reducing time-to-market for integrated circuit (IC) products. This article encompasses the key principles of CADNav for various aspects of semiconductor FA and its importance for improved yield and profitability. An overview of the required input data and formats are described for both IC and package devices, along with key considerations and best practices recommended for fast fault localization, accurate root cause analysis, FA equipment utilization, efficient cross-team collaboration, and database management. Challenges with an FA lab ecosystem are addressed by providing an integrated database and software platform that enable design layout and schematic analysis in the FA lab for quick and accurate navigation and cross-tool collaboration.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

This chapter is a compilation of terms and definitions related to component failure analysis.

Statistics, data analysis, root cause analysis, and problem-solving processes play a key role in failure investigations. This chapter explains how to collect failure investigation data, how to build and maintain a database for company-related failures, and how to use corresponding statistics including type of failure, material, and root cause. It describes the purpose and benefits of conducting a root cause analysis and the factors, namely relative failure importance and company value, that determine when an investigation should be performed. The chapter also discusses the four-step problem-solving process as it applies to failure investigation, how to assemble an investigation team, and the details of organization and planning. It concludes with a case history of the Firestone 500 steel-belted tire failure, stressing the importance of a systematic approach to failure investigations.

There are several analytical methods available that can be used in-line on whole wafers as well as off-line on de-processed products that are returned from the field. These techniques are surface analytical techniques that can be used to characterize the bulk of the material. The main six methods used in semiconductor industry are: Auger spectroscopy, dynamic secondary ion mass spectroscopy, time of flight static secondary ion mass spectroscopy (ToF-SIMS), X-ray photoelectron spectroscopy, scanning electron microscope-energy dispersive X-ray spectroscopy (SEM-EDX), and transmission electron microscope-EDX. This review specifically addresses ToF-SIMS and describes some typical examples of the application of Auger and SEM-EDX.