This chapter reviews various ways to classify failure categories and summarizes the basic types, causes, and mechanisms of damage, with particular consideration given to whether the likelihood of the types of damage can or cannot be influenced by the heat treating of steel parts. The classical organization for types of damage (failures) is as follows: deformation, fracture, wear, corrosion or other environmental damage, and multiple or complex damage. The chapter also provides some examples of lack of conformance to specification that may at first look like the heat treater did something wrong, but where other contributing factors made it difficult or impossible for the heat treater to meet the specification.

The hardenability of steel is governed almost entirely by the chemical composition (carbon and alloy content) at the austenitizing temperature and the austenite grain size at the moment of quenching. This article introduces the methods to evaluate hardenability and the factors that influence steel hardenability and selection. The discussion covers processes involved in Jominy end-quench test for evaluating hardenability. The effect of carbon on hardenability data and the effect of alloys on hardenability during quenching and on the tempering response (after hardening) are also discussed. In addition, the article provides information on the hardenability limits of H-steels after a note on hardenability correlation curves and Jominy equivalence charts.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

This chapter consists of three parts. The first part provides data and guidelines for selecting materials and processing routes. It compares the basic properties of metals, ceramics, and polymers, identifies important measures of performance, and discusses manufacturing processes and their compatibility with specific materials. The chapter then presents general guidelines for selecting lightweight materials, and concludes with a review of lightweight metals, plastics, and composites used in automotive applications.

This article presents methods that enable one to consistently, uniformly and quickly remove substrate silicon from units without imparting damage to the structure of interest. It provides examples of electron beam probing and backside nano-probing techniques. The electron beam probing techniques are E-beam Logic State Imaging, Electron-beam Signal Image Mapping, and E-beam Device Perturbation. Backside nano-probing techniques discussed include: Electron Beam Absorbed Current, Electron Beam Induced Resistance Change, four terminal resistance measurements, resistive gate defect identification, and circuit editing. The article also presents methods to prepare electron beam probing samples where some remaining silicon is required for the transistor functions and transmission electron microscope samples from units where the substrate silicon has been partially or completely removed.

This chapter describes the general characteristics of major types of steel annealing, including the process of normalization, which is a process that refines or normalizes the microstructure of steel. The first part of the chapter begins with an overview of the three-stage process of recovery, recrystallization, and grain growth. This is followed by discussions on annealing processes, namely subcritical annealing, critical-range annealing, full annealing, isothermal annealing, annealing for microstructure, and solution or quench annealing. Next, the chapter describes two undesirable reactions that occur during annealing: decarburization and scaling. Information on the gases and gas mixtures used for controlled atmospheres is then provided. The second part of the chapter focuses on the processes involved in normalizing, along with information on furnace equipment for normalizing. In addition, the chapter includes information on processes involved in induction heating of steel.

This chapter focuses on the inspection of steel bars for the detection and evaluation of flaws. The principles involved also apply, for the most part, to the inspection of steel wire. The nondestructive inspection methods discussed include magnetic particle inspection, liquid penetrant inspection, ultrasonic inspection, and electromagnetic inspection. Eddy current and magnetic permeability are also covered.

This chapter, a detailed account of furnaces and related equipment for heat treating, begins by describing three basic modes of heat transmission, namely conduction, convection, and radiation, followed by a discussion on the working principle, applications, advantages, and disadvantages of furnaces classified based on the heat transfer medium employed. The types of furnaces covered are batch-type, continuous-type, liquid bath, fluidized bed, and vacuum. The subsequent sections provide information on furnace parts, fixtures, quenching mediums, and quenching systems. The final section of the chapter describes the types of atmospheres available, emphasizing their applications and limitations.

The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.

This chapter familiarizes readers with the many and varied thermoset composite fabrication processes and the types of applications for which they were developed. It describes wet lay-up, prepreg lay-up, and low-temperature vacuum bag curing prepreg processes, which are best suited for low-volume, medium-sized and larger parts. It also discusses filament winding and preforming processes (including weaving, knitting, stitching, and braiding) in addition to resin-transfer molding, resin film infusion, and pultrusion.

Cross-sectioning is a technique used for process development and reverse engineering. This article introduces novice analysts to the methods of cross-sectioning semiconductor devices and provides a refresher for the more experienced analysts. Topics covered include encapsulated (potted) device sectioning techniques, non-encapsulated device techniques, utilization of the focused ion beam (FIB) making a cross-section and/or enhancing a physically polished one. Delineation methods for revealing structures are also discussed. These can be chemical etchants, chemo-mechanical polishing, and ion milling, either in the FIB or in a dedicated ion mill.

Optoelectronic components can be readily classified as active light-emitting components (such as semiconductor lasers and light emitting diodes), electrically active but non-emitting components, and inactive components. This chapter focuses on the first category, and particularly on semiconductor lasers. The discussion begins with the basics of semiconductor lasers and the material science behind some causes of device failure. It then covers some of the common failure mechanisms, highlighting the need to identify failures as wearout or maverick failures. The chapter also covers the capabilities of many key optoelectronic failure analysis tools. The final section describes the common steps that should be followed so as to assure product reliability of optoelectronic components.

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

Electronics spans a number of devices, their configurations, and properties. A challenge is to identify those electronic subjects essential for failure analysis. This article reviews the normal operation and terminal characteristics of MOSFET. It describes the electronic behavior of bridges, opens, and parametric delay defects, which is essential for understanding the symptoms of a failing IC. These electronic principles are then applied to a CMOS failure analysis technique using a power supply signature analysis.

There are several analytical methods available that can be used in-line on whole wafers as well as off-line on de-processed products that are returned from the field. These techniques are surface analytical techniques that can be used to characterize the bulk of the material. The main six methods used in semiconductor industry are: Auger spectroscopy, dynamic secondary ion mass spectroscopy, time of flight static secondary ion mass spectroscopy (ToF-SIMS), X-ray photoelectron spectroscopy, scanning electron microscope-energy dispersive X-ray spectroscopy (SEM-EDX), and transmission electron microscope-EDX. This review specifically addresses ToF-SIMS and describes some typical examples of the application of Auger and SEM-EDX.

In the Semiconductor I/C industry, it has been well documented that the proportion of factory and customer field returns attributed to device damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40 to 50%. This study entailed EOS and ESD simulation using a variety of models, namely the Human Body Model (HBM), the Charged Device Model (CDM) and the so-called Machine Model (MM), and then conducting electrical and physical failure analysis and comparing the results with documented analyses performed on customer field returns and factory failures. It is shown that a distinction can be made between EOS and ESD failures and between the characteristic failure signatures produced by the ESD models. The CDM physical failure location is at the input buffer and in the gate oxide, where as both HBM and MM failures occur mostly in the contacts at the input protection structures.

Photon emission (PE) is one of the major optical techniques for contactless isolation of functional faults in integrated circuits (ICs) in full electrical operation. This article describes the fundamental mechanisms of PE in silicon based ICs. It presents the opportunities of contactless characterization for the most important electronic device, the MOS - Field Effect Transistor, the heart of ICs and their basic digital element, the CMOS inverter. The article discusses the specification and selection of detectors for proper PE applications. The main topics are image resolution, sensitivity, and spectral range of the detectors. The article also discusses the value and application of spectral information in the PE signal. It describes state of the art IC technologies. Finally, the article discusses the applications of PE in ICs and also I/O devices, integrated bipolar transistors in BiCMOS technologies, and parasitic bipolar effects like latch up.

This chapter surveys both basic quality and basic reliability concepts as an introduction to the failure analysis professional. It begins with a section describing the distinction between quality and reliability and moves on to provide an overview of the concept of experiment design along with an example. The chapter then discusses the purposes of reliability engineering and introduces four basic statistical distribution functions useful in reliability engineering, namely normal, lognormal, exponential, and Weibull. It also provides information on three fundamental acceleration models used by reliability engineers: Arrhenius, Eyring, and power law models. The chapter concludes with information on failure rates and mechanisms and the two techniques for uncovering reliability issues, namely burn-in and outlier screening.