Search Results for 3D packaging

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

This chapter briefly lays out the challenges associated with electrical fault isolation (EFI) brought on by continued transistor scaling and increasing package complexity. It also identifies high-priority issues and areas of technology that must be addressed for EFI tools and techniques to remain effective.

Time-domain based characterization methods, mainly time-domain reflectometry (TDR) and time-domain transmissometry (TDT), have been used to locate faults in twisted cables, telegraph lines, and connectors in the electrical and telecommunication industry. This article provides a brief review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly made it a well-adopted tool in the industry. The third part of this article introduces a new method which combines impulse signal and the TDT concept, and discusses a combo TDR and TDT method. Cases studies and application notes are shared and discussed for each technique. Application benefits and limitations of these techniques (TDR, EOTPR, and combo TDR/TDT) are summarized and compared.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.

This chapter describes three approaches for 3D hot-spot localization of thermally active defects by lock-in thermography (LIT). In the first section, phase-shift analysis for analyzing stacked die packages is performed. The second example employs defocusing sequences for the localization of resistive electrical shorts in 3D architectures, and the third operates in cross sectional LIT mode to investigate defects in the insulation liner of Through Silicon Vias. All three approaches allow for a precise localization of thermally active defects in all three spatial dimensions to guide subsequent high-resolution physical analyses.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

Magnetic field imaging (MFI), generally understood as mapping the magnetic field of a region or object of interest using magnetic sensors, has been used for fault isolation (FI) in microelectronic circuit failure analysis for almost two decades. Developments in 3D magnetic field analysis have proven the validity of using MFI for 3D FI and 3D current mapping. This article briefly discusses the fundamentals of the technique, paying special attention to critical capabilities like sensitivity and resolution, limitations of the standard technique, sensor requirements and, in particular, the solution to the 3D problem, along with examples of its application to real failures in devices.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

This chapter summarizes critical gaps and long-term needs in failure analysis technology as it relates to logic and memory devices and IC packages. It assesses the impact of vertical integration, new materials, and expansion in the third dimension on volume analysis, sample preparation and measurement methods, and cross-sectioning and imaging.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.