This chapter covers the steps and tests that are important to produce quality parts in heat treating. The quality tests discussed include hardness tests, such as Brinell, Rockwell, and microhardness tests. The chapter also examines tensile testing, toughness testing, optical metallography, and nondestructive testing. The chapter concludes by discussing in-process inspections and the final inspection.

To ensure consistency, quality of results, and documentation compliance, audits are required when heat treating. This chapter introduces basic parts of the ISO certification program.

Planning and laying out casting facilities involve a number of vital factors, such as available infrastructure, selection of suitable sites, orientation of operations and process flow, markets and products, operating parameters, and targeted hourly output and annual capacity. This chapter presents guiding principles and layout concepts with these factors in mind. It also presents steps for the creation of a plant layout. Plant layout involves the arrangement of processing areas, machinery, and equipment for the efficient conversion of raw materials into finished products. The chapter discusses general guidelines for developing a layout.

This chapter assesses the capabilities and limitations of electric fault isolation (EFI) technology, the measurement challenges associated with new device architectures, and the pathways for improvement in emission microscopy, laser stimulation, and optical probing. It also assesses the factors that influence signal strength, spatial and timing resolution, and alignment accuracy between signal response images and the physical layout of the IC.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

This chapter sheds light on the challenges involved in diagnosing faults in analog, mixed-signal, and RF circuits. It describes some of the work being done to leverage the benefits of standardization, improve fault simulation tools, and overcome limitations on optical fault isolation techniques. One of the solutions being considered is to integrate LEDs throughout the analog circuit, thereby using light to report the status of internal signals.

A typical mobile processor die may contain, among other things, a variety of high-performance as well as low-power processing cores along with 5G modems, Wi-Fi modules, image processors, GPUs, and security modules, with a total transistor count exceeding 10 billion. Such designs pose many challenges for yield ramp and diagnostics. This chapter examines these challenges and the growing demand for innovative solutions to help failure analysts quickly and accurately isolate faults. It also assesses the capabilities and future potential of ATPG scan diagnostics, streaming scan networks, and advanced fault models for diagnosing embedded memory.

This chapter assesses the benefits of using a solid immersion lens (SIL) to detect faults in ICs via optical imaging and laser-stimulation techniques. It discusses the advantages and limitations of different types of SILs and their effect on spatial resolution, spot size, focus depth, and collection efficiency. It also provides a brief overview of technical challenges at the die level.

An architectural shift to buried power rails (BPRs) with backside power delivery (BPD) is on the horizon as CMOS technology approaches the 2 nm node. The obstruction created by the presence of BPD networks obsoletes many of the electrical fault isolation (EFI) techniques that have been used for the past few decades and severely degrades the performance of others. This chapter provides an overview of EFI methods that are still applicable to ICs with BPD networks, including e-beam and atomic force probing, x-ray and magnetic field imaging, and lock-in thermography. It assesses the technical challenges of each method as well as the potential for improvement.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

This chapter summarizes critical gaps and long-term needs in failure analysis technology as it relates to logic and memory devices and IC packages. It assesses the impact of vertical integration, new materials, and expansion in the third dimension on volume analysis, sample preparation and measurement methods, and cross-sectioning and imaging.

This chapter provides an overview of key elements in controlling the casting process, systems to confirm the quality of outgoing components, and the steps needed to launch a novel product. The discussion also provides information on process control tools and techniques; incoming material control; process control of sand preparation and system maintenance; metallic charge materials; product quality control; and melting, metallurgical, and mechanical testing.

This chapter surveys both basic quality and basic reliability concepts as an introduction to the failure analysis professional. It begins with a section describing the distinction between quality and reliability and moves on to provide an overview of the concept of experiment design along with an example. The chapter then discusses the purposes of reliability engineering and introduces four basic statistical distribution functions useful in reliability engineering, namely normal, lognormal, exponential, and Weibull. It also provides information on three fundamental acceleration models used by reliability engineers: Arrhenius, Eyring, and power law models. The chapter concludes with information on failure rates and mechanisms and the two techniques for uncovering reliability issues, namely burn-in and outlier screening.

Water chemistry is a factor in nearly all boiler tube failures. It contributes to the formation of scale, biofilms, and sludge, determines deposition rates, and drives the corrosion process. This chapter explains how water chemistry is managed in boilers and describes the effect of impurities and feedwater parameters on high-pressure boiler components. It discusses deposition and scaling, types of corrosion, and carryover, a condition that occurs when steam becomes contaminated with droplets of boiler water. The chapter also covers water treatment procedures, including filtration, chlorination, ion exchange, demineralization, reverse osmosis, caustic and chelant treatment, oxygen scavenging, and colloidal, carbonate, phosphate, and sodium aluminate conditioning.

This chapter concentrates almost exclusively on inspection techniques related to pressure vessels and pipework. The discussion covers the general aspects associated with inspection and the key factors relevant to it. In addition, the chapter addresses processes involved in data collection and management, namely data acquisition, reporting, trending, reviewing, and auditing. Capabilities and limitations of in-service inspection techniques are discussed in the Appendix to this chapter.