The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

This appendix provides a list of etch compositions and procedures that reveal the macrostructure of aluminum, beryllium, bismuth, antimony, cobalt, copper, lead, magnesium, nickel, tin, titanium, zinc, and their respective alloys as well as iron, steel, noble metals, refractory metals, silicon, zirconium, and hafnium.

This appendix lists copper-containing macroetchants that are used on iron and steel.

This appendix lists etch compositions and procedures that reveal strain patterns in aluminum and nickel-base superalloys.

This appendix contains tables that list the composition and capabilities of etchants that reveal the microstructure of metals and alloys, including aluminum, chromium, cobalt, copper, lead, magnesium, molybdenum, nickel, niobium, palladium, platinum, radioactive metals, rare earth metals, rhenium, rhodium, selenium, tellurium, silicon, silver, tantalum, tin, titanium, tungsten, vanadium, and zinc, as well as carbides, oxides, and nitrides.

This appendix is a list of etchants that are used to reveal dislocations in various metals, alloys, and compounds.