This chapter briefly lays out the challenges associated with electrical fault isolation (EFI) brought on by continued transistor scaling and increasing package complexity. It also identifies high-priority issues and areas of technology that must be addressed for EFI tools and techniques to remain effective.

This chapter assesses the capabilities and limitations of electric fault isolation (EFI) technology, the measurement challenges associated with new device architectures, and the pathways for improvement in emission microscopy, laser stimulation, and optical probing. It also assesses the factors that influence signal strength, spatial and timing resolution, and alignment accuracy between signal response images and the physical layout of the IC.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

This chapter sheds light on the challenges involved in diagnosing faults in analog, mixed-signal, and RF circuits. It describes some of the work being done to leverage the benefits of standardization, improve fault simulation tools, and overcome limitations on optical fault isolation techniques. One of the solutions being considered is to integrate LEDs throughout the analog circuit, thereby using light to report the status of internal signals.

A typical mobile processor die may contain, among other things, a variety of high-performance as well as low-power processing cores along with 5G modems, Wi-Fi modules, image processors, GPUs, and security modules, with a total transistor count exceeding 10 billion. Such designs pose many challenges for yield ramp and diagnostics. This chapter examines these challenges and the growing demand for innovative solutions to help failure analysts quickly and accurately isolate faults. It also assesses the capabilities and future potential of ATPG scan diagnostics, streaming scan networks, and advanced fault models for diagnosing embedded memory.

This chapter assesses the benefits of using a solid immersion lens (SIL) to detect faults in ICs via optical imaging and laser-stimulation techniques. It discusses the advantages and limitations of different types of SILs and their effect on spatial resolution, spot size, focus depth, and collection efficiency. It also provides a brief overview of technical challenges at the die level.

An architectural shift to buried power rails (BPRs) with backside power delivery (BPD) is on the horizon as CMOS technology approaches the 2 nm node. The obstruction created by the presence of BPD networks obsoletes many of the electrical fault isolation (EFI) techniques that have been used for the past few decades and severely degrades the performance of others. This chapter provides an overview of EFI methods that are still applicable to ICs with BPD networks, including e-beam and atomic force probing, x-ray and magnetic field imaging, and lock-in thermography. It assesses the technical challenges of each method as well as the potential for improvement.

The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

This chapter summarizes critical gaps and long-term needs in failure analysis technology as it relates to logic and memory devices and IC packages. It assesses the impact of vertical integration, new materials, and expansion in the third dimension on volume analysis, sample preparation and measurement methods, and cross-sectioning and imaging.

This chapter presents the theory and practice associated with the application of thin films. The first half of the chapter describes physical deposition processes in which functional coatings are deposited on component surfaces using mechanical, electromechanical, or thermodynamic techniques. Physical vapor deposition (PVD) techniques include sputtering, e-beam evaporation, arc-PVD, and ion plating and are best suited for elements and compounds with moderate melting points or when a high-purity film is required. The remainder of the chapter covers chemical vapor deposition (CVD) processes, including atomic layer deposition, plasma-enhanced and plasma-assisted CVD, and various forms of vapor-phase epitaxy, which are commonly used for compound films or when deposit purity is less critical. A brief application overview is also presented.

This chapter familiarizes readers with the use of Fick’s laws of diffusion in heat treating, coating, and other metallurgical processes. It contains worked solutions to nearly 30 problems requiring the calculation of activation energy, diffusion coefficient, concentration level, surface layer thickness, case depth, and processing time and temperature. The selected problems deal with various types of iron, steel, and nonferrous alloys and processes ranging from aluminizing, chromizing, carburizing, and plasma nitriding to hydrogen dissipation, decarburizing, and oxidation. A few diffusion problems involving single-crystal silicon are also included.

The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.

Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.

With semiconductor device dimension continuously scaling down and increasing complexity in integrated circuits, delayering techniques for reverse engineering is becoming increasingly challenging. The primary goal of delayering in semiconductor failure analysis is to successfully remove layers of material in order to locate and identify the area of interest. Several of the top-down delayering techniques include wet chemical etching, dry reactive ion etching, top-down parallel lapping (including chemical-mechanical polishing), ion beam milling and laser delayering techniques. This article discusses the general procedure, types, advantages, and disadvantages of each of these techniques. In this article, two types of different semiconductor die level backend of line technologies are presented: aluminum metallization and copper metallization.

Cross-sectioning is a technique used for process development and reverse engineering. This article introduces novice analysts to the methods of cross-sectioning semiconductor devices and provides a refresher for the more experienced analysts. Topics covered include encapsulated (potted) device sectioning techniques, non-encapsulated device techniques, utilization of the focused ion beam (FIB) making a cross-section and/or enhancing a physically polished one. Delineation methods for revealing structures are also discussed. These can be chemical etchants, chemo-mechanical polishing, and ion milling, either in the FIB or in a dedicated ion mill.