This article presents best practices for the metallographic preparation of specimens produced via thermal spray coating methods. It outlines typical metallographic preparation process flow, highlighting important considerations for obtaining a clear and representative specimen suitable for characterization via examination techniques, such as optical or electron microscopy. The process flow includes preliminary resin infiltration, sectioning, mounting, grinding, and polishing. To aid in the identification and resolution of common issues during subsequent specimen analysis, the article presents common issues, along with causes and mitigation strategies. It describes the processes involved in the interpretation of the thermal spray coating microstructure.

Thermal barrier coatings (TBCs) are applied using thermal spray coating (TSC) processes to components that are internally cooled and operated in a heated environment. The TSC microstructures are prone to interactions with common metallographic procedures that may result in artifacts and misinterpretation of the TSC microstructure. This article aims to aid in identifying metallographic TSC artifacts, specifically in the air plasma spray zirconia-based TBC, including both of its common constituents, the bond coating and the top coating. Artifacts that result from specific sectioning and mounting practices, as well as from different polishing times, are presented. Additionally, the article discusses the factors in optical microscopy and scanning electron microscopy that affect microstructure interpretation.

This chapter discusses the principles of scanning transmission electron microscopy (STEM) as implemented using conventional scanning electron microscopes (SEMs). It describes the pros and cons of low-energy imaging and diffraction, addresses basic hardware requirements, and provides information on imaging modes, detector positioning and alignment, and the effect of contrast reversal. It also discusses beam convergence and angular selectivity, the use of application-specific masks, and how to generate grain orientation maps for different material systems.

This chapter discusses the setup and use of a transmission electron detector in a typical scanning electron microscope (SEM). It describes the arrangement and function of the primary components in the detector, following the signal path from the sample to a micromirror array where it is directed by the user to either a CMOS sensor (to record diffraction patterns) or a photomultiplier tube (to observe real-space images). The chapter discusses some of the nuances of digital imaging and diffraction and includes examples in which transmission electron detectors are used to analyze gold films, carbon nanotubes, zeolite sheets, and monolayer graphene. It also describes emerging techniques, including four-dimensional STEM, thermal diffuse scattering, energy filtering, aberration correction, and atomic resolution imaging.

This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.

As semiconductor feature sizes have shrunk, the technology needed to encapsulate modern integrated circuits has expanded. Due to the various industry changes, package failure analyses are becoming much more challenging; a systematic approach is therefore critical. This article proposes a package failure analysis flow for analyzing open and short failures. The flow begins with a review of data on how the device failed and how it was processed. Next, non-destructive techniques are performed to document the condition of the as-received units. The techniques discussed are external optical inspection, X-ray inspection, scanning acoustic microscopy, infrared (IR) microscopy, and electrical verification. The article discusses various fault isolation techniques to tackle the wide array of failure signatures, namely IR lock-in thermography, magnetic current imaging, time domain reflectometry, and electro-optical terahertz pulse reflectometry. The final step is the step-by-step inspection and deprocessing stage that begins once the defect has been imaged.

Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision decapsulation for fine ball grid array packages, accessing the failing die for MCP packages, and careful handling for WLCSP. Solutions and best practices are shared on how to overcome these challenges. The article also presents a few case studies to demonstrate how failure analysis work on CSPs can be successfully completed.

In embedded systems, the separation between system level, board level, and individual component level failure analysis is slowly disappearing. In order to localize the initial defect area, prepare the sample for root cause analysis, and image the exact root cause, the overall functionality has to be maintained during the process. This leads to the requirement of adding additional techniques that help isolate and image defects that are buried deeply within the board structure. This article demonstrates an approach of advanced board level failure analysis by using several non-destructive localization techniques. The techniques considered for advanced fault isolation are magnetic current imaging for shorts and opens; infrared thermography for electrical shorts; time-domain-reflectometry for shorts and opens; scanning acoustic microscopy; and 2D/3D X-Ray microscopy. The individual methods and their operational principles are introduced along with case studies that will show the value of using them on board level defect analysis.

The management of a failure analysis (FA) laboratory requires a broad range of activities to optimize the efficiency of the operation. The purpose of this article is to stimulate readers to consider the various aspects of FA laboratory operations and their respective business management requirements. The various aspects include: staffing, laboratory organization, lab design and operations, strategic development, financial management, and metrics and measurements. References for further reading and examples of resource materials are also included.

Moore's Law has driven many degree circuit features below the resolving capability of optical microscopy. Yet the optical microscope remains a valuable tool in failure analysis. This article describes the physics governing resolution and useful techniques for extracting the small details. It begins with the basic microscope column and construction. The article discusses microscope adjustments, brightfield and darkfield illumination, and microscope concepts important to liquid crystal techniques. It also discusses solid immersion lenses, infrared and ultraviolet microscopy and concludes with laser microscopy techniques such as thermal induced voltage alteration and external induced voltage alteration.

X-ray imaging systems have long played a critical role in failure analysis laboratories. This article begins by listing several favorable traits that make X-rays uniquely well suited for non-destructive evaluation and testing. It then provides information on X-ray equipment and X-ray microscopy and its application in failure analysis of integrated circuit (IC) packaging and IC boards. The final section is devoted to the discussion on nanoscale 3D X-ray microscopy and its applications.

The scanning acoustic microscope (SAM) is an important tool for development of improved molded and flip chip packages. The SAM used for integrated circuit inspection is a hybrid instrument with characteristics of both the Stanford SAM and the C-scan recorder. This chapter presents the historical development of SAM for integrated circuit package inspection, SAM theory, and analysis considerations. Case studies are presented to illustrate the practical applications of SAM. Other non-destructive imaging tools are briefly discussed, as well as SAM challenges and methods including spectral signature analysis and GHz-SAM.

In this overview of diagnosis of scan logic and diagnosis driven failure analysis, the authors explore the world of diagnosis of digital semiconductors devices. After shortly outlining the technology behind diagnosis, the main part of this article describes key improvements to the basic diagnosis tools, discussing their merits for the failure analysis engineer. The article also describes the various requirements and other considerations that typically need to be taken into account to set up a full working scan diagnosis system. It summarizes the principles of design with embedded compression technologies. Finally, several successful industrial applications of diagnosis are presented.

Magnetic field imaging (MFI), generally understood as mapping the magnetic field of a region or object of interest using magnetic sensors, has been used for fault isolation (FI) in microelectronic circuit failure analysis for almost two decades. Developments in 3D magnetic field analysis have proven the validity of using MFI for 3D FI and 3D current mapping. This article briefly discusses the fundamentals of the technique, paying special attention to critical capabilities like sensitivity and resolution, limitations of the standard technique, sensor requirements and, in particular, the solution to the 3D problem, along with examples of its application to real failures in devices.

Time-domain based characterization methods, mainly time-domain reflectometry (TDR) and time-domain transmissometry (TDT), have been used to locate faults in twisted cables, telegraph lines, and connectors in the electrical and telecommunication industry. This article provides a brief review of conventional TDR and its application limitations to advanced packages in semiconductor industry. The article introduces electro optical terahertz pulse reflectometry (EOTPR) and discusses how its improvements of using high frequency impulse signal addressed application challenges and quickly made it a well-adopted tool in the industry. The third part of this article introduces a new method which combines impulse signal and the TDT concept, and discusses a combo TDR and TDT method. Cases studies and application notes are shared and discussed for each technique. Application benefits and limitations of these techniques (TDR, EOTPR, and combo TDR/TDT) are summarized and compared.

The orientation of the devices within a package determine the best chosen approach for access to a select component embedded in epoxy both in package or System in Package and multi-chip module (MCM). This article assists the analyst in making decisions on frontside access using flat lapping, chemical decapsulation, laser ablation, plasma reactive ion etching (RIE), CNC based milling and polishing, or a combination of these coupled with optical or electrical endpoint means. This article discusses the general characteristics, advantages, and disadvantages of each of these techniques. It also presents a case study illustrating the application of CNC milling to isolate MCM leakage failure.

The need for precise targeted interactive surgery on boards or modules is the main driver of backside preparation technology. This article assists the analyst in making decisions on backside thinning and polishing requirements. Thinning of the substrates can be accomplished by flat lapping, laser assisted chemical etch, plasma reactive ion etch, and CNC based milling and polishing. The article discusses the general characteristics, key principles, advantages, and disadvantages of these processes. It also contains case studies that illustrate the application of these processes to ceramic cavity devices, injection molded parts, and ball grid arrays.

Photon emission (PE) is one of the major optical techniques for contactless isolation of functional faults in integrated circuits (ICs) in full electrical operation. This article describes the fundamental mechanisms of PE in silicon based ICs. It presents the opportunities of contactless characterization for the most important electronic device, the MOS - Field Effect Transistor, the heart of ICs and their basic digital element, the CMOS inverter. The article discusses the specification and selection of detectors for proper PE applications. The main topics are image resolution, sensitivity, and spectral range of the detectors. The article also discusses the value and application of spectral information in the PE signal. It describes state of the art IC technologies. Finally, the article discusses the applications of PE in ICs and also I/O devices, integrated bipolar transistors in BiCMOS technologies, and parasitic bipolar effects like latch up.

This article reviews the basic physics behind active photon injection for local photocurrent generation in silicon and thermal laser stimulation along with standard scanning optical microscopy failure analysis tools. The discussion includes several models for understanding the local thermal effects on metallic lines, junctions, and complete devices. The article also provides a description and case study examples of multiple photocurrent and thermal injection techniques. The photocurrent examples are based on Optical Beam-Induced Current and Light-Induced Voltage Alteration. The thermal stimulus examples are Optical Beam-Induced Resistance Change/Thermally-Induced Voltage Alteration and Seebeck Effect Imaging. Lastly, the article discusses the application of solid immersion lenses to improve spatial resolution.