Skip to Main Content
Skip Nav Destination

The complexity of semiconductor chips and their packages has continuously challenged the known methods to analyze them. With larger laminates and the inclusion of multiple stacked die, methods to analyze modern semiconductor products are being pushed toward their limits to support these 2.5D and 3D packages. This article focuses on these methods of fault isolation, non-destructive imaging, and destructive techniques through an iterative process for failure analysis of complex packages.

You do not currently have access to this chapter.
Don't already have an account? Register

or Create an Account

Close Modal
Close Modal