Overview of Wafer-level Electrical Failure Analysis Process for Accelerated Yield Engineering
This article introduces the wafer-level fault localization failure analysis (FA) process flow for an accelerated yield ramp-up of integrated circuits. It discusses the primary design considerations of a fault localization system with an emphasis on complex tester-based applications. The article presents examples that demonstrate the benefits of the enhanced wafer-level FA process. It also introduces the setup of the wafer-level fault localization system. The application of the wafer-level FA process on a 22 nm technology device failing memory test is studied and some common design limitations and their implications are discussed. The article presents a case study and finally introduces a different value-add application flow capitalizing on the wafer-level fault localization system.
S.H. Goh, Y.H. Chan, B.L. Yeoh, H. Hao, M.H. Thor, Z. Lin, C.M. Chua, S.H. Tan, L.S. Koh, W.P. Chua, Overview of Wafer-level Electrical Failure Analysis Process for Accelerated Yield Engineering, Microelectronics Failure Analysis: Desk Reference, 7th ed., Edited By Tejinder Gandhi, ASM International, 2019, p 1–9, https://doi.org/10.31399/asm.tb.mfadr7.t91110001
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