As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.

This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.

This paper describes the effectiveness of using light induced Current Imaging – Atomic Force Microscopy (CIAFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and nongated diode, as a result enhanced localization of gate to source/drain short.

In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

The case study in this paper describes how collaboration between customer design and test teams and a thorough FAB investigation triggered by a detailed electrical analysis using the Atomic Force Nanoprober (AFP) resulted in the effective resolution of a challenging implant related issue on LDMOS structure that caused yield loss. The quick success in this case has led to a shorter yield ramp cycle on this new product for mass production.

This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.

Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.

With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.

Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-SEM de-layering technique over mechanical de-layering is better control of the de-layering process. Combining the precise milling capability of the FIB with the real-time imaging capability of the SEM enables the operator to observe the de-layering as it progresses, minimizing the likelihood of removing either too much or too little material. Furthermore, real time SEM view during top-down XFIB de-layering is able to provide a better understanding of how the defects are formed and these findings could then be feedback to the production line for process improvement.

SEM-based nanoprobing has proven vital in identifying nonvisual failures through electrical characterization in current FA metrology for fault identification. With eight probes used concurrently, the system could have the ability to obtain other important information such as cell stability as well as the static noise margin (SNM). In this work, the cell stability and SNM at different biasing conditions at low electron beam energy (500eV) of a sub-30 nm technology node SRAM device have been characterized. Bit cell stability, static noise margin test as well as leakage study between two adjacent floating wordines were performed on the SRAM samples. Results show that no significant degradation has been introduced during the data acquisition and imaging processes in the SEM. Good resolution imaging with passive voltage contrast can be achieved with low electron voltage (500eV) throughout the nanoprobing process.

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

Rapid technology scaling results in ever shrinking device size. As such, sharper nanotips are required for application in nanoprobing systems. In this work, we present a two-step methodology of fabricating tungsten nanotips with radius of curvature down to 20 nm by using and optimized AC electrochemical etching of tungsten in KOH followed by laser irradiation in KOH. Finally we show the application of the fabricated nanotips with different radius of curvature (ROC) for nanoprobing.

Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.