Although the overall spatial resolution of backscattered electron (BSE) imaging suffers in comparison to secondary electron (SE) imaging, its superior sensitivity to atomic number (Z) contrast and ability to image through overlying insulation levels can provide a complementary approach for imaging subtle buried defects. BSE enables the localization and imaging of embedded defects through overlying insulator levels without the risk of compromising them with reactive ion etch (RIE) or plasma etch exposure or by anisotropic wet chemical delayering process steps. Once the embedded defect is localized with BSE in situ, subsequent imaging by cross sectional Transmission Electron Microscopy (XTEM) combined with elemental analysis by energy dispersive X-Ray analysis (EDX) or electron energy loss spectroscopy (EELs) can be performed without the risk of introducing artifacts. In this work, BSE imaging was successfully employed to image embedded subtle defects in 32nm node technologies through overlying insulator films not possible with conventional SE imaging techniques.

It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.

This paper presents the characterization and analysis of Static Random Access Memory (SRAM) standby leakage by electrical characterization, leakage localization, and atomic force probe (AFP) discrete device probing. The methodology described in the paper was applied on 45 nanometers bulk technology parametric SRAM leakage macros, where it indicated the leakage mechanism was junction leakage in the pullup p-type field effect transistors (PFETs) which resulted in raising the gate voltage on the cross coupled pulldown n-type FETs. Backside Optical Beam Induced Resistance Change using a solid immersion lens was performed to identify the high leakage SRAM cells and nanoprobing with an AFP was used to obtain transistor data, which supported the original leakage mechanism. A SEM cross section was obtained which showed a CArec SRAM cell node contact extending deep into the STI along the side of the PFET active area was the physical cause of the high SRAM standby leakage.

This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.

Bond-pad is an important structure of a microelectronic device because it plays the role of enabling the device to communicate with other external devices. Its integrity directly affects the performance of the microelectronic device. This paper presents our investigation on bond-pad Inter-Metal Dielectric (IMD) crack issue. Our investigation has considered the following factors: top via pattern (sea of vias/without vias) for bond-pad, top metal thickness (8 kÅ /9 kÅ /10 kÅ) and probe overdrive force (30 um/50 um/70 um). The bond-pad IMD cracks were exposed and decorated by chemicals (Aqua Regia and Hydrochloric acid), and inspected by an optical microscope. A scoring system was designed to assess the dependence of the bond-pad IMD crack severity on the above-mentioned factors. The investigation results showed that the IMD crack severity is strongly dependent on the probe overdrive force, top via pattern, and only slightly on top metal thickness.

Process development usually has an indispensable period of yield-learning. The length of the period is highly dependent on identification of the root causes of yield-limiting defects and thus failure analysis plays an important role in the yield improvement process. This paper presents the failure analysis of yield-limiting defects in 0.15µm process development. The failure analysis involves failure mode categorization by MOSAID tester, defective contact identification by contact-level Passive Voltage Contrast (PVC) technique and subsequent Focus Ion Beam (FIB) cross-section followed by Transmission Electron Microscopy (TEM) analysis. Finally, the root causes for the yield-limiting defects were identified.