As semiconductor technology keeps scaling down, the conventional physical failure analysis processes have faced increasing challenges and encountered low success rate. It is not only because the defect causing a failure becomes tinier and tinier, but also because some of these defects themselves are invisible. Electrical nano-probing with narrowing down a defect to a single transistor has greatly increased the likeliness of finding a tiny defect in subsequent TEM (transmission Electron Microscope) analysis. However, there is still an increasing trend of encountering an invisible defect at most advanced technology nodes. This paper will present how to identify the root causes of three such invisible defects with the combination of electrical nano-probing and TEM chemical analysis.

With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.