In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.

During the early stage of process development, the major activities are yield ramp up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and inhouse diagnostics tools for DFT so in case of failure FA procedures are rather simple and standardized: run EDA tool, get fail location, perform pFA then feedback to process engineering. However in the case of marginal failure FA procedures are generally more complicated. FA engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused by many different reasons. The analysis of marginal fail is of course very important to screen out healthy devices and detect any problem of process technology or design methodology. In this paper, the authors deal with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Throughout these case studies, LADA was successfully used to define the fault location. The reason of device alteration was well explained with further study. It is obvious that LADA is a very effective way to analyze marginal failures in cases where the FA engineer doesn’t have much design information because the results are very intuitive and clear. There is little doubt of LADA results accuracy because LADA is utilizing the tester to make an accurate Pass/Fail decision. LADA results are direct indication of device sensitivity to parametric changes, in our case voltage margin.