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Yuk L. Tsang
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Proceedings Papers

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

Yuk L. Tsang, Alex VanVianen, Xiang D. Wang, N. David Theodore
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 205-209, November 9–13, 2014,
https://doi.org/10.31399/asm.cp.istfa2014p0205
Abstract
In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.
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Proceedings Papers

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

Yuk L. Tsang, Xiang D. Wang, Reyhan Ricklefs, Jason Goertz
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 106-111, November 11–15, 2012,
https://doi.org/10.31399/asm.cp.istfa2012p0106
Abstract
In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.
View Papertitled, Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology View PDF for content titled, Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology
Proceedings Papers

Identification of Extension Implant Defect in Sub-Micron CMOS ICs – Analysis Technique, Model, and Solution

Yuk L. Tsang, Giri Nallapati, Ron Skarupa, Brian Anthony
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 212-217, November 13–17, 2011,
https://doi.org/10.31399/asm.cp.istfa2011p0212
Abstract
A major failure mode known as ROMBIST (logic and memory) that topped the yield loss pareto and plagued a 0.13 m technology chipset production was analyzed. This MCUROM fail exhibited a unique failing pattern where every 4th row failed. A detailed electrical microprobing analysis had led to an exact model that was able to explain the failure mechanism. This model pinpointed a PFET extension implant blockage. Subsequent silicon etch analysis directed by the model prediction brought out the non visual defect (NVD). Inline inspection at the extension implant photo step identified the root cause. A greater than 45% reduction in die cost was realized in lots with photo resist fixes implemented.
View Papertitled, Identification of Extension Implant Defect in Sub-Micron CMOS ICs – Analysis Technique, Model, and Solution View PDF for content titled, Identification of Extension Implant Defect in Sub-Micron CMOS ICs – Analysis Technique, Model, and Solution