In wafer fabrication, silicon defects on the substrate directly affect the yield of the wafer. In this paper, we will study and discuss a chemical delayering and delineate method for silicon defects in wafer fabrication using Secco etch. It is well-known that during delayering process of wafer, the removal of polysilicon (Poly-Si) layer is very difficult, especially for the wide-layer polysilicon (Poly-Si) which is difficult to completely remove with HF acid solution. We introduce a chemical recipe to fast delayer polysilicon layer completely before delineating silicon defects on silicon substrate using Secco etch. Those skilled in the art could be experiment within half an hour to get analysis results. It saves time and improves operational efficiency. Moreover, based on the experimental results we think that it is possible to identify the root cause according to the shapes of silicon defects using Secco etch.

Currently, wire bonding is still the dominant interconnection mode in microelectronic packaging, and epoxy molding compound (EMC) is the major encapsulant material. Normally EMC contains chlorine (Cl) and sulfur (S) ions. It is important to understand the control limit of Cl and S in the EMC to ensure good Au wire bond reliability. This paper discussed the influences of Cl and S on the Au wire bond. Different contents of Cl and S were purposely added into the EMC. Accelerated reliability tests were performed to understand the effects of Cl, S and their contents on the Au wire bond reliability. Failure analysis has been conducted to study the failure mechanism. It is found that Cl reacted with IMCs under humid environment. Cl also caused wire bond failure in HTS test without moisture. On the other hand, the results showed that S was not a corrosive ion. It was also not a catalyst to the Au bond corrosion. Whilst, high content of S remain on the bond pad hindered the IMCs formation and caused earlier failure of the wire bond.

In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

In this work, we discussed the fault isolation method for the Thin-Film Transistor (TFT). Many defects in the TFT can be directly observed by optical microscope; however, some defects are not visible in either optical microscope or SEM making the fault isolation effort very challenging. We demonstrated that OBIRCH can be used to find defect locations in TFT failures for leakage and shorts. The TFT is so fragile that the laser power and biasing voltage have to be very carefully controlled to avoid damaging the TFT. After identifying the defect location by OBIRCH hot spot detection, the defect was successfully captured with TEM analysis.

The Rotation Averaged Spectrum of TEM diffraction patterns can be sharpened by a Maximum-Likelihood deconvolution algorithm. The sharpened spectrum will help to improve the precision of TEM diffraction-based techniques, e.g.: phase identification and strain analysis.

In this study, a comprehensive investigation of the Ag-Al bond degradation mechanism in an electrically failed module using the argon ion milling, scanning electron microscopy (SEM), dual beam focused ion beam-SEM, scanning transmission electron microscopy energy dispersive x-ray spectroscopy, and time-of-flight secondary ion mass spectrometry is reported. It is found that the bond degradation is due to the galvanic corrosion in the Ag-Al bonding area. Specific attention is given to the information of microstructures, elements, and corrosive ions in the degraded bond. In this study, it is believed that the Ag-Al bond degradation is highly related to the packaging designs.

In wafer fabrication, Fluorine (F) contamination may cause fluorine-induced corrosion and defects on microchip Aluminum (Al) bondpads, resulting in bondpad discoloration or non-stick on pads (NSOP). Auger Electron Spectroscopy (AES) is employed for measurements of the fluorine level on the Al bondpads. From a Process control limit and a specification limit perspective, it is necessary to establish a control limit to enable process monitor reasons. Control limits are typically lower than the specification limits which are related to bondpad quality. The bondpad quality affects the die bondability. This paper proposes a simulation method to determine the specification limit of Fluorine and a Shelf Lifetime Accelerated Test (SLAT) for process monitoring. Wafers with different F levels were selected to perform SLAT with high temperature and high relative humidity tests for a fixed duration to simulate a one year wafer storage condition. The results of these simulation results agree with published values. If the F level on bondpad surfaces was less than 6.0 atomic percent (at%), then no F induced corrosion on the bond pads was observed by AES. Similarly, if the F level on bond pad surfaces was higher than 6.0 atomic per cent (at%) then AES measured F induced corrosion was observed.

Contamination in the gate oxide layer is the most common effect which cause the gate oxide integrate (GOI) issue. Dynamic Secondary Ion Mass Spectrometry (SIMS) is a mature tool for GOI contamination analysis. During the sample preparation, all metal and IDL layers above poly should be removed because the presence of these layers added complexity for the subsequent SIMS analysis. The normal delayering process is simply carried out by soaking the sample in the HF solution. However, the poly surface is inevitably contaminated by surroundings even though it is already a practice to clean with DI rinse and tape. In this article, TOFSIMS with low energy sputter gun is used to clean the sample surface after the normal delayering process. The residue signals also can be monitored by TOF SIMS during sputtering to confirm the cross contamination is cleared. After that, a much lower background desirable by dynamic SIMS. Thus an accurate depth profile in gate oxide layer can be achieved without the interference from surface.

This paper described a gate oxide failure case which affected the electrical parameters such as Vt and Idsat of both HV N&P MOS. A systematic problem solving approach combined with several FA techniques was applied to find the root-cause to be arsenic outgas cross-contamination.

Threshold Voltage (Vt) of MOSFET controls transistor’s on and off state. Vt is usually depends on gate oxide thickness and operating temperature. Systematic failure analysis for a Vt shift issue, should also consider the channel doping which affects the inversion layer formation. In this article, the failure case of a shift in the Vt of a Power MOSFET V is studied. Secondary Ion Mass Spectrometry (SIMS) is found to be the most direct way for detecting any abnormality in the channel doping profiles. A comprehensive simulation is performed showing that the Phosphorus level diffusion from substrate was so high that it affects the doping concentration of channel.

The distribution of Si nanoparticles, both dimensional and spatial, is a key factor affecting the performance of non-volatile flash memory devices. A new FIB method has been developed to prepare ultra-thin plan view specimens, containing only the Si nanoparticle matrix thin film layer, from fully processed nanocrystalline flash memory devices. The morphology and distribution of Si nanoparticles were then studied by EFTEM 3D tomographic reconstruction.

In this paper, two failure analysis case studies are presented to demonstrate the importance of sample preparation procedures to successful failure analyses. Case study 1 establishes that Palladium (Pd) cannot be used as pre-FIB coating for SiO2 thickness measurement due to the spontaneously Pd silicide formation at the SiO2/Si interface. Platinum (Pt) is thus recommended, in spite of the Pt/SiO2 interface roughness, as the pre-FIB coating in this application. In the second case study, the dual-directional TEM inspection method is applied to characterize the profile of the “invisible” tungsten residue defect. The tungsten residue appears invisible in the planeview specimen due to the low mass-thickness contrast. It is then revealed in the cross-sectional TEM inspection.