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Youmin Kim
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 157-160, October 28–November 1, 2024,
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As dynamic random access memory (DRAM) chips grow in density and complexity, tightly packed word lines become increasingly susceptible to interference, potentially causing data retention failures. This study investigates a novel failure mechanism where disconnected buried channel array transistors (BCATs) create interference affecting three adjacent word lines (3row failure). Through systematic analysis of voltage, temperature, and operational sequences, we demonstrate that the pass gate effect significantly impairs dynamic data retention, leading to these 3row failures. Our findings reveal a previously unidentified defect mechanism in advanced DRAM technology and emphasize the importance of comprehensive testing protocols for detecting and characterizing emerging failure modes. This work contributes to the broader effort of improving DRAM reliability in modern computing systems.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 62-66, November 12–16, 2023,
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Device shrinkage and mitigation of off-state power consumption are crucial factors in dynamic random access memory (DRAM) product development. Given the market demand for high-quality devices, the reduction and fluctuation of DRAM cell retention time, caused by interface traps, required a suitable solution for improved product quality. In this study, we propose a device structure for the reduction of GIDL current by implementing a second gate oxide in the overlapping region of the gate and the drain, and to calculate an increment in the margin for other processes from the retention time improvements, the virtual a capacitance of the bit line/a capacitance of the storage cap(Cb/Cs) evaluation was performed. This study is expected to provide a solution to the trap-induced retention- time deterioration and assist in the development of next-generation DRAM.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 411-413, October 30–November 3, 2022,
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As devices shrink, mitigating off-state power consumption has become a major concern for dynamic random access memory (DRAM) product development. The interface trap induced reduction of the retention time of DRAM cells has become increasingly critical due to aggressive device shrinkage. In this paper, the influence of reliability evaluation after device manufacturing on the number of interface traps in buried-channel-array-transistors and the optimal H 2 annealing temperature were investigated for the reduction of trap-induced leakage currents that cause retention time degradation in DRAM cells. This study is expected to solve the problem of retention time and off-state power consumption caused by interface traps and to be utilized as a cornerstone for next-generation DRAM development.