A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.