Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.

Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.

Cross-sectional polishing has been widely used in the semiconductor industry. As demand for higher throughput increases, the time spent manually performing a final polish is an improper method for cross-section preparation. Etching is the major function of Precise Etching and Coating System (PECS). In this article, the focus is on Ar plasma cleaning performance on a sample after rough polishing and a sample after a short time final polishing using PECS. To evaluate performance of Ar plasma cleaning, two samples were prepared for SEM observation. X-SEM images before and after Ar plasma cleaning revealed that Ar plasma cleaning is not an effective method to correct micro scratches. The combination of final polishing and stain into one step was found to improve sample quality and throughput. PECS Ar plasma was found to be an effective sample cleaning method when compared to the time spent on final polishing.

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

In this paper, the deformation mechanism of low K dielectric film under electron beams (E-beams) is discussed, and the effect of film deformation on the development of a low K dielectric film etching recipe is investigated. To provide meaningful data for process development, numerical analysis was used in the failure analysis procedure. A correction factor is formulated to calculate the change in thickness of the low K dielectric film after E-beam exposure. In addition, scanning electron microscope (SEM) settings for imaging low K dielectric films are optimized to minimize deformation.