This paper presents a new method for improving the quality and effectiveness of scan-based tests. The method, called statistical diagnosis, leverages defect likelihoods learned from analyzing populations of failing die instead of analyzing each die independently as traditionally done. The method was validated in a large silicon study that showed significant improvement in diagnosis resolution with minimal impact on diagnosis accuracy. Statistical diagnosis, as the paper explains, can also be used to predict or identify the dominant defect mechanism in low yielding wafers.

Electrical failure analysis (EFA) is usually time consuming and expensive. It is a critical step bridging data failure analysis (DFA) and physical failure analysis (PFA). This paper presents experiments on using volume scan diagnosis as a component in building up an efficient EFA solution for digital circuits and discusses practical considerations in the production yield flow. It provides a brief review of the existing methods and the requirement to build an efficient flow, followed by a discussion on the proposed solution. The proposed solution can be used systematically in different stages of the production yield flow. The paper then shows industrial case studies and their results and benefits.

If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.

Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.

Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

In this paper, DACS stands for Defects that Affect Chain and System, which could be any type of silicon defects caused by an unintentional interaction between a scan chain signal and a system logic signal. The device could fail scan chain testing or show up as a latent failure in the customer’s system. A novel diagnosis methodology is proposed to locate both ends of a DACS. The proposed algorithm can be generally applied to any type of DACS. Experimental results on industrial chips demonstrate the effectiveness of the proposed method.