Unique frequency dependent hold time violation debug seen on Ethernet IP that caused at least 50% yield loss is showcased in this paper. This debug exposed the process variation issue seen, limitation in current FPGA timing sign-off methodology and design limitation that led to this rare hold time behavior. Customized ATPG patterns has become de facto for effective HVM screening including exploration of new path hold time fault pattern generation. The debug was backed by tester level and system validation debug with help from optical probing and FIB to confirm the root cause and silicon fixes required.

It has been a challenge to perform failure analysis for miniaturization of process node technology in high-speed transceiver. Failure analysis plays an important role in root cause analysis to enable R&D, product quality & reliabily improvement. This paper demonstrated an effective FA approach on a real case with ADPLL functional failure within a high-Speed transceiver in complex sub-nano FPGA. This successful case is achieved by incorporating Analog Probe (APROBE), Infrared Emission Microscopy (IREM), extensive layout study, delayering, Nanoprobing and Scanning Electron Microscopy (SEM) for defect localization.