As semiconductor devices continue to decrease in size and pitch, demands for accurate microstructural analysis have increased to enable downward scaling. Critical dimension (CD) metrology is key to delivering process insights, but at such scales, rigorous metrology analysis providing high precision data may lack desired throughput. CD measurement using the scanning electron microscope (SEM) is a widely used technique, however, to acquire large area SEM images with high precision, multiple image stitching is currently required. In this paper, a new method for precise and efficient metrology analysis is introduced. This study demonstrates that large area imaging with ultra-high pixel resolution can deliver better throughput while maintaining the same level of precision that can be achieved by the traditional method.

Scanning Electron Microscope (SEM) is a valuable tool for measuring Critical Dimensions (CD) of semiconductor devices at the nanometer scale. Vertical SEM application is one of the applications for high accurate CD measurement on cross-sectional surface. Even a slight stage tilt angle change of the vertical sample can impact CD values in nanometer scales of the sample surface features. For accurate CD measurements, it is essential to ensure the sample is positioned correctly to acquire the sample image. However, it is challenging to achieve a perfect alignment with the incident beam direction and the accurate perpendicular direction on the cross-sectional surface on SEM tool. To achieve an ideal vertical positioning of the sample, the combination of the stage tilt axis and stage rotation axis can be used. Exact calculation is required to achieve an accurate CD measurement. In this paper, a calculation method of the tilt angle correction to achieve a perpendicular angle to the surface and its verification method are described. Reliable measurement can be achieved by employing an automated script for compensation. We also demonstrate an approach for highly reliable angle correction and improved metrology results in this paper.

In this paper, we propose a method to get more accurate metrology data using the tilt-axis on a transmission electron microscope (TEM) to compensate for microscopic tilt-axis changes that occur during focused ion beam (FIB) sample preparation processing. This method was developed using V-NAND plan-view samples which require channel hole measurements for each layer to support process monitoring. To test this method, we obtained the same image by progressively tilting the alpha and beta axes one degree in the positive and negative direction using a V-NAND planar sample. The strongest contrast edge was found by contrast profile analysis of each edge of the V-NAND channel using automated software. Through this method, we were able to optimize the sample position and automate the process to capture high quality images to accurately measure V-NAND channel holes. The details are discussed in this paper.

Focused ion beam (FIB) microscopy is an essential technique for the site-specific sample preparation of atom probe tomography (APT). The site specific APT and automated APT sample preparation by FIB have allowed increased APT sample volume. In the workflow of APT sampling, it is very critical to control depth of the sample where exact region of interest (ROI) for accurate APT analysis. Very precise depth control is required at low kV cleaning process in order to remove the damaged layer by previous high kV FIB process steps. We found low kV cleaning process with 5 kV and followed by 2kV beam conditions delivers better control to reached exact ROI on Z direction. This understanding is key to make APT sample with fully automated fashion.

The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.