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William Lo
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Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2023
DOI: 10.31399/asm.tb.edfatr.t56090091
EISBN: 978-1-62708-462-8
Abstract
An architectural shift to buried power rails (BPRs) with backside power delivery (BPD) is on the horizon as CMOS technology approaches the 2 nm node. The obstruction created by the presence of BPD networks obsoletes many of the electrical fault isolation (EFI) techniques that have been used for the past few decades and severely degrades the performance of others. This chapter provides an overview of EFI methods that are still applicable to ICs with BPD networks, including e-beam and atomic force probing, x-ray and magnetic field imaging, and lock-in thermography. It assesses the technical challenges of each method as well as the potential for improvement.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 153-162, October 30–November 3, 2022,
Abstract
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Near Infra-Red (NIR) techniques such as Laser Voltage Probing/Imaging (LVP/I), Dynamic Laser Stimulation (DLS), and Photon Emission Microscopy (PEM) are indispensable for Electrical Fault Isolation/Electrical Failure Analysis (EFI/EFA) of silicon Integrated Circuit (IC) devices. However, upcoming IC architectures based on Buried Power Rails (BPR) with Backside Power Delivery (BPD) networks will greatly reduce the usefulness of these techniques due to the presence of NIR-opaque layers that block access to the transistor active layer. Alternative techniques capable of penetrating these opaque layers are therefore of great interest. Recent developments in intense, focused X-ray microbeams for micro X-Ray Fluorescence (μXRF) microscopy open the possibility to using X-rays for targeted and intentional device alteration. In this paper, we will present results from our preliminary investigations into X-ray Device Alteration (XDA) of flip-chip packaged FinFET devices and discuss some implications of our findings for EFI/EFA.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 116-121, November 15–19, 2020,
Abstract
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Working on wafer-level has been the only way of performing electrical failure analysis (EFA) without the need for die-packaging. The introduction of Si-interposer based 2.5D packaging, with high bandwidth memory (HBM) stacks surrounding our GPU chip, drastically increasing packaging turn around times from approximately 3 days to 3-4 weeks. Having to wait more than 3 weeks for EFA and debug work of 1st Silicon chips is a significant risk for chip bring-up. To address these challenges, this paper presents different ways of reusing the existing wafer-level EFA tool for single die EFA, and introduces a concept for a novel and dedicated single die tool. Additionally, singulated die fixturing and support windows are designed to enable the usage of a 2.45 Numerical Aperture Solid Immersion Lens, and first results from a near reticle limited 16 nm Fin-FET GPU product are also presented.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 86-98, November 10–14, 2019,
Abstract
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High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 7-18, November 6–10, 2016,
Abstract
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Using a laser to purposely damage (or zap) a static random-access memory (SRAM) bitcell for bitmap validation purposes is a well-established technique. However, the absence of visible damage in FinFET SRAM cells, amongst other things, makes precision zapping in these devices more difficult. In this paper, we describe system enhancements and a modified workflow for bitmap validation of these devices using precision, near-infrared (NIR) laser-induced damage. We also explore the use of laser perturbation and non-precision zapping options. Examples are provided.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 161-165, November 6–10, 2016,
Abstract
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Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2015) 17 (2): 4–9.
Published: 01 May 2015
Abstract
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This is the second article in a two-part series that explains how to measure the performance of solid immersion lenses (SILs) used for backside imaging and analysis. In Part I, published in the February 2015 issue of EDFA , the authors describe how they modified a frontside metrology target and used it to evaluate a SIL in a backside imaging system, which prompted the development of an unmounted, backside-specific version of the through-silicon target. In Part II, they explain how these new targets, in addition to measuring resolution, are being used to determine the field of view as well as the line spread and edge response of backside imaging systems. They also discuss some of the challenges encountered when using the targets to characterize emission microscopy systems.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2015) 17 (1): 12–20.
Published: 01 February 2015
Abstract
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Metrology targets are an essential tool for evaluating the performance of imaging systems and maintaining their accuracy over time. Ideally, the pattern on the target is simple enough that the expected image is intuitive or, at least, easily simulated. Although many such targets exist for frontside imaging, until recently, few if any could be found for backside applications. In this article, the first of a two-part series, the authors explain how they addressed this gap by converting a readily available frontside target for backside use. The conversion process is described step by step in enough detail that it can be replicated in order to convert other frontside targets. Due to the success of the converted target, an unmounted, backside-specific version has subsequently been developed, the availability of which not only eliminates one of the more difficult steps in the original conversion process, but also provides additional benefits. Using one of these newer targets, the authors evaluated a backside imaging system consisting of a laser scanning microscope (LSM) and a solid immersion lens (SIL). The results are presented here along with the criteria used for the evaluation. Other applications of the new metrology target as well as its limitations are discussed in the May 2015 issue of EDFA .
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 12-17, November 13–17, 2011,
Abstract
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A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 249-255, November 2–6, 2008,
Abstract
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We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 9-17, November 14–18, 2004,
Abstract
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A novel laser based technique for waveform probing of integrated circuits is presented. This new technique exploits polarization-dependent opto-electronic effects in silicon integrated circuits to give phase sensitivity via a simple common-path interferometer design. The system utilizes a 10 ps pulse-width mode-locked laser to generate equivalent-time sampling pulses. A custom wavelength-tunable and spectrally matched external-cavity laser diode source is used for noise cancellation. A 20-GHz intrinsic system bandwidth with a 2x lower noise-floor, in comparison to current laser voltage probing technology, is shown.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 753-762, November 3–7, 2002,
Abstract
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Time-resolved photon emission (TRPE) results, obtained using a new superconducting, single-photon detector (SSPD) are reported. Detection efficiency (DE) for large area detectors has recently been improved by >100x without affecting SSPDs inherently low jitter (≈30 ps) and low dark-count rate (<30 s-1). TRPE measurements taken from a 0.13 μm geometry CMOS IC are presented. A single laser, time-differential probing scheme that is being investigated for next-generation laser voltage probing (LVP) is also discussed. This new scheme is designed to have shot-noise-limited performance, allowing signals as small as 100 parts-per-million (ppm) to be reliably measured.
Proceedings Papers
ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 479-485, November 12–16, 2000,
Abstract
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Single probe beam phase-sensitive detection has been applied to backside optical probing using an interferometer with a novel vibration cancellation scheme. Improved waveform quality and consistency, compared to amplitude-sensitive detection, has been successfully demonstrated on a number of CMOS microprocessors based on the 0.18 um logic process technology. The interferometric probing scheme will be described in detail and results will be presented.