With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

On older semiconductor technology, electron-beam probing (EBP) for active voltage contrast and waveform on frontside metal lines was widely utilized. EBP is also being extended to include the well-known optical techniques such as signal mapping imaging (SMI) with the use of a lock-in amplifier in the signal chain and e-beam device perturbation. This paper highlights some of the achievements from an Intel in-house built e-beam tool on current technology nodes. The discussion covers the demonstration of fin and contact resolution on the current technology nodes by EBP and the analysis of the SRAM array with EBP and EBP of metal lines. By utilizing EBP, it has been demonstrated that logic state imaging, SMI, and waveform have significantly improved spatial resolution compared to the current optical fault isolation analogues.

A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.

As device dimensions continue to shrink, process defects tend to become more subtle. For most failure analysis (FA) studies, it is important to identify the defect location for the subsequent material analysis. To achieve this, nano-probing has been widely used in the FA community. Copper (Cu) contacts posed a significant challenge to nano-probing since Cu is soft and tends to deform during measurements. In addition, Cu oxidizes quickly in air, increasing contact resistance significantly between the probes and devices. This paper introduces electroless cobalt (Co) plating on Cu contacts for nano-probing to overcome these technical problems. As Cu is soft and oxidized quickly in air, the technique presented in this paper provides a technical solution for nano-probing on Cu contacts. With carefully characterized Co plating time, this technique can be used not only on Cu contacts but also on Cu interconnection.