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Wen-Tung Chang
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Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 46-48, November 6–10, 2005,
Abstract
View Papertitled, Failure Analysis of Soft Single Column Failure in Advanced Nano SRAM Device with Internal Probing Techniques
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for content titled, Failure Analysis of Soft Single Column Failure in Advanced Nano SRAM Device with Internal Probing Techniques
Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 101-105, November 3–7, 2002,
Abstract
View Papertitled, Applications of EELS to Semiconductor Devices Failure Analysis by Using a 300 keV TEM
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for content titled, Applications of EELS to Semiconductor Devices Failure Analysis by Using a 300 keV TEM
A 300 keV TEM equipped with an EELS and energy selected imaging (ESI) system has proven to be a necessary and powerful analytical tool for R&D and failure analysis support. The advantages and the efficacy of this advanced elemental mapping technique can be optimized when the TEM is operated correctly. Variants of ESI, elemental mapping, jump-ratio mapping, and pre-edge imaging have been adapted to explore root causes of different type of failures in semiconductor manufacturing.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 393-396, November 11–15, 2001,
Abstract
View Papertitled, The Preparation Method of ULSI Sample With Photoresist for TEM Analysis
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for content titled, The Preparation Method of ULSI Sample With Photoresist for TEM Analysis
This paper describes a novel method of sample preparation for Transmission Electron Microscope (TEM) analysis, particularly a technique for photoresist sample preparation for TEM analysis. In the analysis of an ultra large scale integrated (ULSI) circuit, the profile images of a ULSI circuit sample are crucial. In order to identify the tiny features of modern semiconductor devices clearly, TEMs are used because of their high spatial resolution. However, TEM analysis is not available for photoresist material, especially for a patterned photoresist layer, due to the difficulty in specimen preparation and its susceptibility to electron beam damage during TEM analysis. A critical step in preparing this type of TEM specimens is to deposit a conductive layer and a dielectric layer upon the patterned phototresist by a physical vapor deposition process at room temperature first, then followed by a focus ion beam (FIB) process. The exact profile of the patterned photoresist is kept, during specimen preparation and TEM analysis, by this modified method. Precise dimension measurements are then possible.