A new application of the Novel Dielectric Etch solution for FIB Circuit Edit is reported to allow smooth and fast removal of copper dummies/dielectric layers for exposure of the circuitry underneath. Experimental data on the selectivity of the removal of dummies as a function of the ion beam current density is provided. Examples of de-processing several layers to expose a line of interest as well as the exposure of fine copper lines beneath the copper dummies/dielectric layer are presented.

A novel solution is presented for dielectric and silicon etching when using FIB for circuit edit. In contrast to commonly used XeF2, the new solution has a significantly higher activation threshold that allows it to be used for etching new sensitive low-k dielectrics and even thin silicon without the risk of damaging these materials spontaneously. Examples of operations presented are: etching through ultra low-k dielectrics on a front side device, exposure of a conductor through shallow trench isolation (STI), and trimming active silicon when performing circuit edit on a back side device. The advantages in comparison to XeF2 applications are discussed.

The ability to edit a circuit in silicon quickly and confidently is extremely valuable as it permits verification of changes or fixes without the need to generate new reticles and fabricate new silicon. However, dramatic changes in the material used in IC’s combined with the downward scaling of dimensions required the development of a scalable process not only in three dimensions but also in material. Details of this process and results are presented in this paper.