Miniaturization of today’s semiconductor devices and increased complexity of transistor architecture have resulted in gradually shrinking defect sizes. A direct consequence to this is the diminished chance of catching defects in the Transmission Electron Microscope (TEM) on the initial lamella, prompting the need to convert the TEM lamellas to analyze them from a different angle. In this work, a reliable step-by-step procedure to perform in-situ TEM lamella conversion is detailed. The applicability of the method is successfully validated on defective sub-20nm FinFET samples. Two different initial lamella types –planar and cross-sectional – are featured in the case studies to demonstrate the method’s versatility.

Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.