A sample preparation technique for flip chips (FC) deprocessing from the back side proposed. The technique uses HNA chemistry (consisting of a mixture of acids: hydrofluoric, nitric and acetic) to wet-etch the heavily-boron-doped Si bulk substrate selectively to the lightly-boron-doped Si epi. The procedure can be used as a FC device sample preparation technique for back-side optical probing and FIB editing.

High frequency signal propagation through transmission lines has been an important discipline for RF engineers. With advancements in digital technologies, especially when data rates reached multiple Gb/s, package designers have to consider parameters such as transmission loss and trace impedance in order to maintain signal integrity. For high frequency signals, the surface roughness of the copper trace becomes increasingly significant in determining conduction loss, due to current confinement to the conductor surface by the skin effect. Accurate 3D conductor surface maps are required for correct trace insertion loss simulation. Practical methods for package trace exposure and 3D surface height map acquisition are discussed in this paper. Advantages and disadvantages of these methods, and their implementation to real packages are shown. Using electrical parameters resulting from a 3D trace surface map, the error between electrical simulations and actual measurements of insertion loss in an FCBGA package have been reduced from 6% to nearly zero, enabling tighter margins in 10GB/s high speed serial design.

Bond-pad integrity directly affects the performance of microelectronic devices. Bond-pad cracking and the related sub-pad cracking of Inter-Metal Dielectric (IMD) may introduce a high reliability risk and cause units to fail at environmental stress. Bond-pad cracks may be initiated by probing during wafer sort and the wire bonding process during assembly. This paper presents a comparative analysis of the various chemistries used for exposure and decoration of pad cracks. The investigation showed that a tri-iodine etch provides clean and artifact-free exposure of the TiN barrier layer of the pad and is the best (of the methods tried herein) for pad crack observation.

A robust procedure for poly-silicon wet etch selective to SiO2 is presented. The procedure is applicable for CMOS devices and maintains the integrity of the gate oxide film. The technique uses a 50% wt. choline hydroxide aqueous solution. The optimum etching conditions, which allow exposure of gate oxide to enable its further inspection using SEM or AFM were determined. An investigation of general silicon etching characteristics of choline hydroxide, as etch rate, selectivity and surface quality, has been carried out as well.