As the Internet of Things, smart factories and autonomous driving increase the demand for low-price radar sensors, the authors address this need by developing a 24 GHz short range radar in standard bulk silicon CMOS technology for mass market production. CMOS technology enables cost reduction and efficient system integration compared to former GaAs and current SiGe solutions. Design for failure analysis (DFFA) is implemented in the low-noise amplifier (LNA) of the radar to identify and compensate process deviations. It consists of scalable capacitor structures and is executed using focused ion beam circuit edit. By doing so, the design specifications of high gain and low noise of the LNA are reliably met at high yield for the desired operating frequency. The presented DFFA method enables a shift in peak gain by 2.5 GHz. It thereby improves gain and noise figure at 24 GHz by 2 dB and -0.2 dB respectively. The resulting optimized LNA achieves a gain of 20 dB and a noise figure of 3.7 dB matching and surpassing other state-of-the-art works in a single prototyping run.

Optical spatial resolution improvement using local focused ion beam (FIB) assisted silicon material removal was investigated. Two types of test structures were chosen for imaging-resolution characterization to be able to use two ways of measuring resolution. Samples of various remaining bulk silicon thicknesses were prepared and characterized in terms of image quality and spatial resolution. The resulting remaining bulk Si thickness was measured using reflectance spectrometry. Images were acquired using halogen-lamp illumination and reflected light detection using a cooled Si-CCD detector. To investigate the image quality at various wavelengths, a set of interference band-pass filters was applied.

Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.